Contents
Contents
1
Introduction....................................................................................................................................11
1.1
Terminology........................................................................................................................12
1.1.1 Processor Packaging Terminology ........................................................................12
References .........................................................................................................................13
1.2
2
Electrical Specifications.................................................................................................................15
2.1
2.2
2.3
FSB and GTLREF...............................................................................................................15
Power and Ground Lands...................................................................................................15
Decoupling Guidelines........................................................................................................15
2.3.1 VCC Decoupling ....................................................................................................16
2.3.2 FSB GTL+ Decoupling...........................................................................................16
2.3.3 FSB Clock (BCLK[1:0]) and Processor Clocking ...................................................16
Voltage Identification ..........................................................................................................17
2.4.1 Phase Lock Loop (PLL) Power and Filter ..............................................................19
Reserved, Unused, FC and TESTHI Signals......................................................................20
FSB Signal Groups.............................................................................................................21
GTL+ Asynchronous Signals ..............................................................................................22
Test Access Port (TAP) Connection...................................................................................23
FSB Frequency Select Signals (BSEL[2:0]) .......................................................................23
2.4
2.5
2.6
2.7
2.8
2.9
2.10 Absolute Maximum and Minimum Ratings .........................................................................24
2.11 Processor DC Specifications ..............................................................................................24
2.12 VCC Overshoot Specification .............................................................................................33
2.12.1 Die Voltage Validation ...........................................................................................33
2.13 GTL+ FSB Specifications....................................................................................................34
3
Package Mechanical Specifications ..............................................................................................35
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Package Mechanical Drawing ............................................................................................35
Processor Component Keep-Out Zones.............................................................................39
Package Loading Specifications.........................................................................................39
Package Handling Guidelines.............................................................................................39
Package Insertion Specifications........................................................................................40
Processor Mass Specification.............................................................................................40
Processor Materials............................................................................................................40
Processor Markings............................................................................................................40
Processor Land Coordinates ..............................................................................................41
4
5
Land Listing and Signal Descriptions ............................................................................................43
4.1
4.2
Processor Land Assignments.............................................................................................43
Alphabetical Signals Reference..........................................................................................66
Thermal Specifications and Design Considerations......................................................................75
5.1
5.2
Processor Thermal Specifications ......................................................................................75
5.1.1 Thermal Specifications ..........................................................................................75
5.1.2 Thermal Metrology.................................................................................................79
Processor Thermal Features ..............................................................................................79
5.2.1 Thermal Monitor.....................................................................................................79
5.2.2 Thermal Monitor 2..................................................................................................80
Datasheet
3
INTEL [ INTEL ]
