41210 Bridge — Datasheet
Table 3.
PCI Interface Pins (Sheet 2 of 2)
Signal
I/O
Description
A_PCIXCAP
B_PCIXCAP
PCI-X Capable: Indicates whether all devices on the PCI bus are PCI-X devices, so that the 41210
Bridge can switch into PCI-X mode. Use an approximately 8.2KΩ resistor to pull to VCC33.
I
PCI Lock: Indicates an exclusive bus operation and may require multiple transactions to complete.
This signal is an output from the bridge when it is initiating exclusive transactions on PCI. LOCK# is
ignored when PCI masters are granted the bus. Locked transaction do not propagate upstream.
A_LOCK#
B_LOCK#
O
No External pull-up resistors are required on the system board for these signals.
Total
118
2.4
PCI Bus Interface 64-Bit Extension (Two Interfaces)
Table 4.
PCI Interface Pins: 64-Bit Extensions
Signal
I/O
Description
PCI Address/Data: These signals are a multiplexed address and data bus. This bus provides an
additional 32 bits to the PCI bus. During the data phases of a transaction, the initiator drives the
upper 32 bits of 64-bit write data, or the target drives the upper 32 bits of 64-bit read data, when
REQ64# and ACK64# are both asserted.
A_AD[63:32]
B_AD[63:32]
I/O
Bus Command and Byte enables upper 4 bits: These signals are a multiplexed command field and
byte enable field. For both reads and write transactions, the initiator will drive byte enables for the
AD[63:32] data bits on C/BE7:4] during the data phases when REQ64# and ACK64# are both
A_C/BE#[7:4]
B_C/BE#[7:4]
I/O
asserted.
A_PAR64
B_PAR64
PCI interface upper 32 bits parity: This carries the even parity of the 36 bits of AD[63:32] and C/
BE#[7:4] for both address and data phases.
I/O
I/O
PCI interface request 64-bit transfer: This is asserted by the initiator to indicate that the initiator is
requesting a 64-bit data transfer. It has the same timing as FRAME#. When the 41210 Bridge is
the initiator, this signal is an output. When the 41210 Bridge is the target this signal is an input.
A_REQ64#
B_REQ64#
PCI interface acknowledge 64-bit transfer: This is asserted by the target only when REQ64# is
asserted by the initiator, to indicate the target ability to transfer data using 64 bits. It has the same
timing as DEVSEL#.
A_ACK64#
B_ACK64#
I/O
78
Total
12
INTEL [ INTEL ]
