Datasheet — 41210 Bridge
Table 3.
PCI Interface Pins (Sheet 1 of 2)
Signal
I/O
Description
PCI Address/Data: These signals are a multiplexed address and data bus. During the address
phase or phases of a transaction, the initiator drives a physical address on X_AD[31:0]. During the
data phases of a transaction, the initiator drives write data, or the target drives read data.
A_AD[31:0]
B_AD[31:0]
I/O
I/O
No External pull-up resistors are required on the system board for these signals.
Bus Command and Byte Enables: These signals are a multiplexed command field and byte enable
field. During the address phase or phases of a transaction, the initiator drives the transaction type on
C/BE#[3:0]. When there are two address phases, the first address phase carries the dual address
command and the second address phase carries the transaction type. For both read and write
transactions, the initiator drives byte enables on C/BE#[3:0] during the data phases.
A_C/BE#[3:0]
B_C/BE#[3:0]
No External pull-up resistors are required on the system board for these signals.
Parity: Even parity calculated on 36 bits - AD[31:0] plus C/BE[3:0]#. It is calculated on all 36 bits
regardless of the valid byte enables. It is generated for address and data phases. It is driven
identically to the AD[31:0] lines, except it is delayed by exactly one PCI clock. It is an output during
the address phase for all 41210 Bridge initiated transactions and all data phases when the 41210
Bridge is the initiator of a PCI write transaction, and when it is the target of a read transaction.
A_PAR
B_PAR
I/O
I/O
41210 Bridge checks parity when it is the initiator of PCI read transactions and when it is the target of
PCI write transactions.
No External pull-up resistors are required on the system board for these signals.
Device Select: The bridge asserts DEVSEL# to claim a PCI transaction. As a target, the 41210 Bridge
asserts DEVSEL# when a PCI master peripheral attempts an access an address destined for PCI
Express. As an initiator, DEVSEL# indicates the response to a 41210 Bridge initiated transaction on the
PCI bus. DEVSEL# is tri-stated from the leading edge of PCIRST#. DEVSEL# remains tri-stated by
the 41210 Bridge until driven as a target.
A_DEVSEL#
B_DEVSEL#
No External pull-up resistors are required on the system board for these signals.
Frame: FRAME# is driven by the Initiator to indicate the beginning and duration of an access. While
FRAME# is asserted data transfers continue. When FRAME# is negated the transaction is in the final
data phase.
A_FRAME#
B_FRAME#
I/O
I/O
No External pull-up resistors are required on the system board for these signals.
Initiator Ready: IRDY# indicates the ability of the initiator to complete the current data phase of the
transaction. A data phase is completed when both IRDY# and TRDY# are sampled asserted.
A_IRDY#
B_IRDY#
No External pull-up resistors are required on the system board for these signals.
Target Ready: Indicates the ability of the target to complete the current data phase of the transaction.
A data phase is completed when both TRDY# and IRDY# are sampled asserted. TRDY# is tri-stated
from the leading edge of RST#. TRDY# remains tri-stated by the 41210 Bridge until driven as a target.
A_TRDY#
B_TRDY#
I/O
I/O
I/O
No External pull-up resistors are required on the system board for these signals.
Stop: Indicates that the target is requesting an initiator to stop the current transaction.
A_STOP#
B_STOP#
No External pull-up resistors are required on the system board for these signals.
Parity Error: Driven by an external PCI device when it receives data that has a parity error. Driven by
41210 Bridge when, as a initiator it detects a parity error during a read transaction and as a target
during write transactions.
A_PERR#
B_PERR#
No External pull-up resistors are required on the system board for these signals.
System Error: The 41210 Bridge samples SERR# as an input and conditionally forwards it to the
A_SERR#
B_SERR#
PCI Express.
I
No External pull-up resistors are required on the system board for these signals.
66 MHz Enable: This input signal from the PCI Bus indicates the speed of the PCI Bus. If it is high
then the Bus speed is 66 MHz and if it is low then the bus speed is 33 MHz. This signal will be used
to generate appropriate clock (33 or 66 MHz) on the PCI Bus.
A_M66EN
B_M66EN
I/OD
Use an approximately 8.2KΩ resistor to pull to VCC33 or pull-down to ground.
11
INTEL [ INTEL ]
