2.13.3
2.13.4
2.13.5
2.13.6
2.13.7
SC_IO_LATENCY_C0—IO Latency configuration Register .........................242
TC_SRFTP_C0–Self Refresh Timing Parameters Register .........................242
PM_PDWN_config_C0–Power-down Configuration Register ......................243
TC_RFP_C0—Refresh Parameters Register.............................................244
TC_RFTP_C0—Refresh Timing Parameters Register.................................244
2.14 MCHBAR Registers in Memory Controller – Channel 1 ...........................................245
2.14.1
2.14.2
2.14.3
2.14.4
2.14.5
2.14.6
2.14.7
TC_DBP_C1—Timing of DDR – Bin Parameters Register ..........................245
TC_RAP_C1—Timing of DDR – Regular Access Parameters Register ..........246
SC_IO_LATENCY_C1—IO Latency configuration Register .........................247
PM_PDWN_config_C1—Power-down Configuration Register .....................248
TC_RFP_C1—Refresh Parameters Register.............................................249
TC_RFTP_C1—Refresh Timing Parameters Register.................................250
TC_SRFTP_C1—Self refresh Timing Parameters Register .........................250
2.15 MCHBAR Registers in Memory Controller –
Integrated Memory Peripheral Hub (IMPH) ..........................................................251
2.15.1
2.15.2
CRDTCTL3—Credit Control 3 Register ...................................................251
CRDTCTL4—Credit Control 4 Register ...................................................252
2.16 MCHBAR Registers in Memory Controller – Common.............................................253
2.16.1
2.16.2
2.16.3
2.16.4
MAD_CHNL—Address Decoder Channel Configuration Register.................253
MAD_DIMM_ch0—Address Decode Channel 0 Register............................254
MAD_DIMM_ch1—Address Decode Channel 1 Register............................255
PM_SREF_config—Self Refresh Configuration Register.............................256
2.17 Memory Controller MMIO Registers Broadcast Group Registers...............................257
2.17.1
2.17.2
2.17.3
PM_PDWN_config—Power-down Configuration Register...........................258
PM_CMD_PWR—Power Management Command Power Register................259
PM_BW_LIMIT_CONFIG—BW Limit Configuration Register .......................259
2.18 Integrated Graphics VTd Remapping Engine Registers ..........................................260
2.18.1
2.18.2
2.18.3
2.18.4
2.18.5
2.18.6
2.18.7
2.18.8
2.18.9
VER_REG—Version Register ................................................................261
CAP_REG—Capability Register.............................................................262
ECAP_REG—Extended Capability Register .............................................266
GCMD_REG—Global Command Register................................................267
GSTS_REG—Global Status Register......................................................271
RTADDR_REG—Root-Entry Table Address Register .................................272
CCMD_REG—Context Command Register ..............................................273
FSTS_REG—Fault Status Register ........................................................275
FECTL_REG—Fault Event Control Register .............................................277
2.18.10 FEDATA_REG—Fault Event Data Register ..............................................278
2.18.11 FEADDR_REG—Fault Event Address Register .........................................278
2.18.12 FEUADDR_REG—Fault Event Upper Address Register..............................278
2.18.13 AFLOG_REG—Advanced Fault Log Register............................................279
2.18.14 PMEN_REG—Protected Memory Enable Register.....................................280
2.18.15 PLMBASE_REG—Protected Low-Memory Base Register............................281
2.18.16 PLMLIMIT_REG—Protected Low-Memory Limit Register ...........................282
2.18.17 PHMBASE_REG—Protected High-Memory Base Register ..........................283
2.18.18 PHMLIMIT_REG—Protected High-Memory Limit Register..........................284
2.18.19 IQH_REG—Invalidation Queue Head Register.........................................285
2.18.20 IQT_REG—Invalidation Queue Tail Register ...........................................285
2.18.21 IQA_REG—Invalidation Queue Address Register.....................................286
2.18.22 ICS_REG—Invalidation Completion Status Register ................................286
2.18.23 IECTL_REG—Invalidation Event Control Register....................................287
2.18.24 IEDATA_REG—Invalidation Event Data Register .....................................288
2.18.25 IEADDR_REG—Invalidation Event Address Register ................................288
2.18.26 IEUADDR_REG—Invalidation Event Upper Address Register.....................289
2.18.27 IRTA_REG—Interrupt Remapping Table Address Register ........................289
2.18.28 IVA_REG—Invalidate Address Register..................................................290
2.18.29 IOTLB_REG—IOTLB Invalidate Register.................................................291
8
Datasheet, Volume 2
INTEL [ INTEL ]
