Features
7.5.8.3
APFF: Additional Processor Feature Flags
This location contains additional feature information from the processor. Writes to this
register have no effect.
Offset:
Bit
71h
Description
7
6
5
4
3
2
1
0
Reserved
Intel® Cache Safe Technology
Extended Halt State (C1E)
Intel® Virtualization Technology
Execute Disable
®
Intel 64
®
Intel Thermal Monitor 2
®
Enhanced Intel SpeedStep Technology
Bits are set when a feature is present, and cleared when they are not.
7.5.8.4
MPSUP: Multiprocessor Support
This location contains 2 bits for representing the supported number of physical
processors on the bus. These two bits are LSB aligned where 00b equates to non-
scalable 2 socket (2S) operation, 01b to scalable 2 socket (S2S), 10 to scalable 4
socket (S4S), and scalable 8 socket (S8S). Intel Xeon Processor E7-8800/4800/2800
Product Families processor is a S2S, S4S, or S8S processor. The first six bits in this field
are reserved for future use. Writes to this register have no effect.
Example: A scalable 8 socket processor will have a value of 03h at offset 71h.
Offset:
72h
Bit
Description
7:2
RESERVED
000000b-111111b: Reserved
1:0
Multiprocessor Support
2S, S2S, S4S or S8S indicator
00b: Non-Scalable 2 Socket
01b: Scalable 2 Socket
10b: Scalable 4 Socket
11b: Scalable 8 Socket
7.5.8.5
TCDC: Tap Chain Device Count
At offset 73, a 4-bit hex digit is used to tell how many devices are in the TAP Chain.
Because the Intel Xeon Processor E7-8800/4800/2800 Product Families processor has
ten cores, this field would be set to Ah.
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