Features
7.5.7.5
TRDCKS: Thermal Reference Data Checksum
This location provides the checksum of the Thermal Reference Data Section. Writes to
this register have no effect.
Offset:
6Bh
Bit
Description
7:0
Thermal Reference Data Checksum
One-byte checksum of the of Thermal Reference Data Checksum
00h- FFh: See Section 7.5.10 for calculation of this value.
7.5.8
Feature Data
This section provides information on key features that the platform may need to
understand without powering on the processor.
7.5.8.1
PCFF: Processor Core Feature Flags
This location contains a copy of results in EDX[31:0] from Function 1 of the CPUID
instruction. These details provide instruction and feature support by product family.
Writes to this register have no effect.
Example: A value of BFEBFBFFh can be found at offset 6C - 6Fh.
Offset:
6Ch-6Fh
Bit
Description
31:0
Processor Core Feature Flags
00000000h-FFFFFFFFF: Feature Flags
7.5.8.2
PFF: Processor Feature Flags
This location contains additional feature information from the processor. Writes to this
register have no effect.
Note:
Bit 5 and Bit 6 are mutually exclusive (only one bit will be set).
Offset:
Bit
70h
Description
7
6
5
4
3
2
1
0
Multi-Core (set if the processor is a multi-core processor)
Serial signature (set if there is a serial signature at offset 5B- 62h)
Electronic signature present (set if there is a electronic signature at 5B- 62h)
Thermal Sense Device present (set if an SMBus thermal sensor is on package)
Reserved
OEM EEPROM present (set if there is a scratch ROM at offset 80 - FFh)
Core VID present (set if there is a VID provided by the processor)
L3 Cache present (set if there is a level-3 cache on the processor)
Bits are set when a feature is present, and cleared when they are not.
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