Thermal Specifications
It should be noted that assertion of FORCE_PR_N does not automatically assert
PROCHOT_N. As mentioned previously, the PROCHOT_N signal is asserted when a high
temperature situation is detected. A minimum pulse width of 500 µs is recommended
when FORCE_PR_N is asserted by the system. Sustained activation of the FORCE_PR_N
signal may cause noticeable platform performance degradation.
6.2.7
THERMTRIP_N Signal
Regardless of whether or not the Intel Thermal Monitor 1 or 2 is enabled, in the event
of a catastrophic cooling failure, the processor will automatically shut down when any
core has reached an elevated temperature (refer to the THERMTRIP_N definition in
Table 5-1). At this point, the sideband signal THERMTRIP_N will go active and stay
active as described in Table 5-1. THERMTRIP_N activation is independent of processor
activity. If THERMTRIP_N is asserted, processor core voltage (VCC) and processor cache
voltage (Vcache) must be removed within the time frame defined.
This signal is only valid when power good is asserted, and CPU reset is not asserted.
6.2.8
THERMALERT_N Signal
The THERMALERT_N pin activates when a pre-programmed temperature is reached on
any of the device cores. This pre-programmed temperature is an offset from Prochot,
an programmed via BIOS. There is no sign for the value, as it is always assumed that
the values is less than or equal to Prochot. When not programmed, the value is zero.
The expected usage for this signal is in fan speed control when direct PECI readings are
not used. Note that all thermal specifications must be met when using this signal as
part of an over all thermal solution.
This signal is only valid when power good is asserted, CPU reset is not asserted, and
BIOS has configured the THERMALERT threshold temperature. Note that BIOS can not
configure the THERMALERT threshold until the processor is out of reset.
6.3
Platform Environment Control Interface (PECI)
The Platform Environment Control Interface (PECI) uses a single wire for self-clocking
and data transfer. The bus requires no additional control lines. The physical layer is a
self-clocked one-wire bus that begins each bit with a driven, rising edge from an idle
level near zero volts. The duration of the signal driven high depends on whether the bit
value is a logic ‘0’ or logic ‘1’. PECI also includes variable data transfer rate established
with every message. In this way, it is highly flexible even though underlying logic is
simple.
The interface design was optimized for interfacing to Intel® processor and chipset
components in both single processor and multiple processor environments. The single
wire interface provides low board routing overhead for the multiple load connections in
the congested routing area near the processor and chipset components. Bus speed,
error checking, and low protocol overhead provides adequate link bandwidth and
reliability to transfer critical device operating conditions and configuration information.
The PECI bus offers:
• A wide speed range from 2 Kbps to 2 Mbps
• CRC check byte used to efficiently and atomically confirm accurate data delivery
• Synchronization at the beginning of every message minimizes device timing
accuracy requirements
Datasheet Volume 1 of 2
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