Pin Listing and Signal Descriptions
Table 4-3. Signal Description (Sheet 2 of 8)
Name
Type
Description
BINIT# (Bus Initialization) may be observed and driven by all processor FSB
agents and if used, must connect the appropriate pins of all such agents. If the
BINIT# driver is enabled during power-on configuration, BINIT# is asserted to
signal any bus condition that prevents reliable future operation.
If BINIT# observation is enabled during power-on configuration, and BINIT# is
sampled asserted, symmetric agents reset their bus LOCK# activity and bus
request arbitration state machines. The bus agents do not reset their IOQ and
transaction tracking state machines upon observation of BINIT# activation. Once
the BINIT# assertion has been observed, the bus agents will re-arbitrate for the
FSB and attempt completion of their bus queue and IOQ entries.
Input/
Output
BINIT#
If BINIT# observation is disabled during power-on configuration, a central agent
may handle an assertion of BINIT# as appropriate to the error handling
architecture of the system.
BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is
unable to accept new bus transactions. During a bus stall, the current bus owner
cannot issue any new transactions.
Input/
Output
BNR#
This input is required to determine whether the processor is installed in a
platform that supports the Celeron D processor. The Celeron D processor will not
operate if this pin is low. This input has a weak internal pull-up.
BOOTSELECT
Input
BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor
signals. They are outputs from the processor which indicate the status of
breakpoints and programmable counters used for monitoring processor
performance. BPM[5:0]# should connect the appropriate pins of all Celeron D
processor FSB agents.
BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is
a processor output used by debug tools to determine processor debug
readiness.
Input/
Output
BPM[5:0]#
BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ#
is used by debug tools to request debug operation of the processor.
Refer to the applicable chipset platform design guide for more detailed
information.
These signals do not have on-die termination. Refer to Section 2.5, and the
applicable chipset platform design guide for termination requirements.
BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor
FSB. It must connect the appropriate pins of all processor FSB agents.
Observing BPRI# active (as asserted by the priority agent) causes all other
agents to stop issuing new requests, unless such requests are part of an
ongoing locked operation. The priority agent keeps BPRI# asserted until all of its
requests are completed, then releases the bus by de-asserting BPRI#.
BPRI#
BR0#
Input
BR0# (Bus Request 0) drives the BREQ0# signal in the system and is used by
the processor to request the bus. During power-on configuration this pin is
sampled to determine the agent ID = 0.
Input/
Output
This signal does not have on-die termination and must be terminated.
The BCLK[1:0] frequency select signals BSEL[1:0] are used to select the
processor input clock frequency. Table 2-6 defines the possible combinations of
the signals and the frequency associated with each combination. The required
BSEL[1:0]
Output frequency is determined by the processor, chipset and clock synthesizer. All
agents must operate at the same frequency. For more information about these
pins, including termination recommendations refer to Section 2.9 and the
appropriate platform design guidelines.
COMP[1:0] must be terminated on the system board using precision resistors.
Analog Refer to the applicable chipset platform design guide for details on
implementation.
COMP[1:0]
Datasheet
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INTEL [ INTEL ]
