Electrical Specifications
2 Electrical Specifications
This chapter describes the electrical characteristics of the processor interfaces and signals. DC
electrical characteristics are provided.
2.1
FSB and GTLREF
Most Celeron D processor FSB signals use Gunning Transceiver Logic (GTL+) signaling
technology. The termination voltage level for the Celeron D processor GTL+ signals is VCC, which
is the operating voltage of the processor core. Because of the speed improvements to data and
address bus, signal integrity and platform design methods have become more critical than with
previous processor families.
The GTL+ inputs require a reference voltage (GTLREF) that is used by the receivers to determine
if a signal is a logical 0 or a logical 1. GTLREF must be generated on the system board
(see Table 2-18 for GTLREF specifications). Termination resistors are provided on the processor
silicon and are terminated to its core voltage (VCC). Intel chipsets will also provide on-die
termination, thus eliminating the need to terminate the bus on the system board for most GTL+
signals.
Some GTL+ signals do not include on-die termination and must be terminated on the system board.
See Table 2-4 for details regarding these signals.
The GTL+ bus depends on incident wave switching. Therefore, timing calculations for GTL+
signals are based on flight time instead of capacitive deratings. Analog signal simulation of the
FSB, including trace lengths, is highly recommended when designing a system.
2.2
2.3
Power and Ground Pins
For clean on-chip power distribution, the Celeron D processor has 85 VCC (power) and 179 VSS
(ground) pins. All power pins must be connected to VCC, while all VSS pins must be connected to
a system ground plane.The processor VCC pins must be supplied by the voltage determined by the
VID (Voltage identification) pins.
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is capable of
generating large current swings between low and full power states. This may cause voltages on
power planes to sag below their minimum values if bulk decoupling is not adequate. Care must be
taken in the board design to ensure that the voltage provided to the processor remains within the
specifications listed in Table 2-8. Failure to do so can result in timing violations or reduced lifetime
of the component. For further information and design guidelines, refer to the applicable VRD
design guide.
Datasheet
15
INTEL [ INTEL ]
