Functional Description
5.19.12 Function Level Reset Support (FLR)
The USB EHCI Controllers support the Function Level Reset (FLR) capability. The FLR
capability can be used in conjunction with Intel Virtualization Technology. FLR allows an
Operating System in a Virtual Machine to have complete control over a device,
including its initialization, without interfering with the rest of the platform. The device
provides a software interface that enables the Operating System to reset the whole
device as if a PCI reset was asserted.
5.19.12.1 FLR Steps
5.19.12.1.1 FLR Initialization
1. A FLR is initiated by software writing a ‘1’ to the Initiate FLR bit.
2. All subsequent requests targeting the Function will not be claimed and will be
Master Abort Immediate on the bus. This includes any configuration, I/O or
Memory cycles, however, the Function shall continue to accept completions
targeting the Function.
5.19.12.1.2 FLR Operation
The Function will Reset all configuration, I/O and memory registers of the Function
except those indicated otherwise and reset all internal states of the Function to the
default or initial condition.
5.19.12.1.3 FLR Completion
The Initiate FLR bit is reset (cleared) when the FLR reset is completed. This bit can be
used to indicate to the software that the FLR reset is completed.
Note:
From the time Initiate FLR bit is written to 1, software must wait at least 100 ms before
accessing the function.
5.20
SMBus Controller (D31:F3)
The ICH10 provides an System Management Bus (SMBus) 2.0 host controller as well as
an SMBus Slave Interface. The host controller provides a mechanism for the processor
to initiate communications with SMBus peripherals (slaves). The ICH10 is also capable
of operating in a mode in which it can communicate with I2C compatible devices.
The ICH10 can perform SMBus messages with either packet error checking (PEC)
enabled or disabled. The actual PEC calculation and checking is performed in hardware
by the ICH10.
The Slave Interface allows an external master to read from or write to the ICH10. Write
cycles can be used to cause certain events or pass messages, and the read cycles can
be used to determine the state of various status bits. The ICH10’s internal host
controller cannot access the ICH10’s internal Slave Interface.
The ICH10 SMBus logic exists in Device 31:Function 3 configuration space, and consists
of a transmit data path, and host controller. The transmit data path provides the data
flow logic needed to implement the seven different SMBus command protocols and is
controlled by the host controller. The ICH10 SMBus controller logic is clocked by RTC
clock.
The SMBus Address Resolution Protocol (ARP) is supported by using the existing host
controller commands through software, except for the new Host Notify command
(which is actually a received message).
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Datasheet
INTEL [ INTEL ]
