14.1.14SCNL_BAR—Secondary Control Block Base Address
Register (IDE D31:F1)...........................................................................508
14.1.15BAR — Legacy Bus Master Base Address Register
(SATA–D31:F2)....................................................................................509
14.1.16ABAR/SIDPBA1 — AHCI Base Address Register/Serial ATA Index
Data Pair Base Address (SATA–D31:F2)...................................................509
14.1.17SVID—Subsystem Vendor Identification Register
(SATA–D31:F2)....................................................................................510
14.1.18SID—Subsystem Identification Register (SATA–D31:F2).............................510
14.1.19CAP—Capabilities Pointer Register (SATA–D31:F2)....................................510
14.1.20INT_LN—Interrupt Line Register (SATA–D31:F2).......................................511
14.1.21INT_PN—Interrupt Pin Register (SATA–D31:F2)........................................511
14.1.22IDE_TIM — IDE Timing Register (SATA–D31:F2).......................................511
14.1.23PID—PCI Power Management Capability Identification
Register (SATA–D31:F2)........................................................................511
14.1.24PC—PCI Power Management Capabilities Register
(SATA–D31:F2)....................................................................................512
14.1.25PMCS—PCI Power Management Control and Status
Register (SATA–D31:F2)........................................................................512
14.1.26MSICI—Message Signaled Interrupt Capability Identification
(SATA–D31:F2)....................................................................................513
14.1.27MSIMC—Message Signaled Interrupt Message Control (SATA–D31:F2).........514
14.1.28MSIMA— Message Signaled Interrupt Message Address (SATA–D31:F2).......515
14.1.29MSIMD—Message Signaled Interrupt Message Data (SATA–D31:F2) ............515
14.1.30MAP—Address Map Register (SATA–D31:F2).............................................516
14.1.31PCS—Port Control and Status Register (SATA–D31:F2) ..............................516
14.1.32SCLKCG—SATA Clock Gating Control Register...........................................519
14.1.33SCLKGC—SATA Clock General Configuration Register.................................520
14.1.34FLRCID—FLR Capability ID (SATA–D31:F2) ..............................................522
14.1.35FLRCLV—FLR Capability Length and Version (SATA–D31:F2).......................522
14.1.36FLRC—FLR Control (SATA–D31:F2) .........................................................523
14.1.37ATC—APM Trapping Control Register (SATA–D31:F2).................................523
14.1.38ATS—APM Trapping Status Register (SATA–D31:F2)..................................524
14.1.39SP Scratch Pad Register (SATA–D31:F2)..................................................524
14.1.40BFCS—BIST FIS Control/Status Register (SATA–D31:F2) ...........................525
14.1.41BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2) ........................527
14.1.42BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2) ........................527
14.2 Bus Master IDE I/O Registers (D31:F2)...............................................................528
14.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F2) ..........................529
14.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F2)................................530
14.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer
Register (D31:F2).................................................................................531
14.2.4 AIR—AHCI Index Register (D31:F2) ........................................................531
14.2.5 AIDR—AHCI Index Data Register (D31:F2)...............................................531
14.3 Serial ATA Index/Data Pair Superset Registers.....................................................532
14.3.1 SINDX – Serial ATA Index (D31:F2) ........................................................532
14.3.2 SDATA – Serial ATA Data (D31:F2) .........................................................532
14.4 AHCI Registers (D31:F2) ..................................................................................536
14.4.1 AHCI Generic Host Control Registers (D31:F2)..........................................537
14.4.2 Vendor Specific Registers (D31:F2).........................................................545
14.4.3 Port Registers (D31:F2).........................................................................545
15
SATA Controller Registers (D31:F5) .......................................................................563
15.1 PCI Configuration Registers (SATA–D31:F5)........................................................563
15.1.1 VID—Vendor Identification Register (SATA—D31:F5).................................564
15.1.2 DID—Device Identification Register (SATA—D31:F5) .................................565
15.1.3 PCICMD—PCI Command Register (SATA–D31:F5) .....................................565
15.1.4 PCISTS — PCI Status Register (SATA–D31:F5) .........................................566
15.1.5 RID—Revision Identification Register (SATA—D31:F5) ...............................566
15.1.6 PI—Programming Interface Register (SATA–D31:F5) .................................567
15.1.7 SCC—Sub Class Code Register (SATA–D31:F5).........................................567
15.1.8 BCC—Base Class Code Register (SATA–D31:F5)........................................567
15.1.9 PMLT—Primary Master Latency Timer Register
(SATA–D31:F5)....................................................................................568
15.1.10PCMD_BAR—Primary Command Block Base Address
Register (SATA–D31:F5)........................................................................568
12
Datasheet
INTEL [ INTEL ]
