13.1.25GEN3_DEC—LPC I/F Generic Decode Range 3 Register
(LPC I/F—D31:F0) ................................................................................402
13.1.26GEN4_DEC—LPC I/F Generic Decode Range 4 Register
(LPC I/F—D31:F0) ................................................................................403
13.1.27LGMR — LPC I/F Generic Memory Range (LPC I/F—D31:F0)
(Corporate Only) ..................................................................................403
13.1.28FWH_SEL1—Firmware Hub Select 1 Register (LPC I/F—D31:F0)..................404
13.1.29FWH_SEL2—Firmware Hub Select 2 Register (LPC I/F—D31:F0)..................405
13.1.30FWH_DEC_EN1—Firmware Hub Decode Enable Register
(LPC I/F—D31:F0) ................................................................................406
13.1.31BIOS_CNTL—BIOS Control Register (LPC I/F—D31:F0) ..............................408
13.1.32FDCAP—Feature Detection Capability ID (LPC I/F—D31:F0)........................409
13.1.33FDLEN—Feature Detection Capability Length (LPC I/F—D31:F0)..................409
13.1.34FDVER—Feature Detection Version (LPC I/F—D31:F0) ...............................409
13.1.35FDVCT—Feature Vector (LPC I/F—D31:F0)...............................................410
13.1.36RCBA—Root Complex Base Address Register (LPC I/F—D31:F0)..................410
13.2 DMA I/O Registers (LPC I/F—D31:F0).................................................................411
13.2.1 DMABASE_CA—DMA Base and Current Address
Registers (LPC I/F—D31:F0)...................................................................412
13.2.2 DMABASE_CC—DMA Base and Current Count Registers
(LPC I/F—D31:F0) ................................................................................413
13.2.3 DMAMEM_LP—DMA Memory Low Page Registers
(LPC I/F—D31:F0) ................................................................................413
13.2.4 DMACMD—DMA Command Register (LPC I/F—D31:F0) ..............................414
13.2.5 DMASTA—DMA Status Register (LPC I/F—D31:F0) ....................................414
13.2.6 DMA_WRSMSK—DMA Write Single Mask Register
(LPC I/F—D31:F0) ................................................................................415
13.2.7 DMACH_MODE—DMA Channel Mode Register
(LPC I/F—D31:F0) ................................................................................416
13.2.8 DMA Clear Byte Pointer Register (LPC I/F—D31:F0)...................................417
13.2.9 DMA Master Clear Register (LPC I/F—D31:F0) ..........................................417
13.2.10DMA_CLMSK—DMA Clear Mask Register (LPC I/F—D31:F0) ........................417
13.2.11DMA_WRMSK—DMA Write All Mask Register
(LPC I/F—D31:F0) ................................................................................418
13.3 Timer I/O Registers (LPC I/F—D31:F0) ...............................................................419
13.3.1 TCW—Timer Control Word Register (LPC I/F—D31:F0)...............................420
13.3.2 SBYTE_FMT—Interval Timer Status Byte Format Register
(LPC I/F—D31:F0) ................................................................................422
13.3.3 Counter Access Ports Register (LPC I/F—D31:F0)......................................423
13.4 8259 Interrupt Controller (PIC) Registers
(LPC I/F—D31:F0) ...........................................................................................424
13.4.1 Interrupt Controller I/O MAP (LPC I/F—D31:F0)........................................424
13.4.2 ICW1—Initialization Command Word 1 Register
(LPC I/F—D31:F0) ................................................................................425
13.4.3 ICW2—Initialization Command Word 2 Register
(LPC I/F—D31:F0) ................................................................................426
13.4.4 ICW3—Master Controller Initialization Command
Word 3 Register (LPC I/F—D31:F0).........................................................427
13.4.5 ICW3—Slave Controller Initialization Command
Word 3 Register (LPC I/F—D31:F0).........................................................427
13.4.6 ICW4—Initialization Command Word 4 Register
(LPC I/F—D31:F0) ................................................................................428
13.4.7 OCW1—Operational Control Word 1 (Interrupt Mask)
Register (LPC I/F—D31:F0)....................................................................428
13.4.8 OCW2—Operational Control Word 2 Register
(LPC I/F—D31:F0) ................................................................................429
13.4.9 OCW3—Operational Control Word 3 Register
(LPC I/F—D31:F0) ................................................................................430
13.4.10ELCR1—Master Controller Edge/Level Triggered Register
(LPC I/F—D31:F0) ................................................................................431
13.4.11ELCR2—Slave Controller Edge/Level Triggered Register
(LPC I/F—D31:F0) ................................................................................432
13.5 Advanced Programmable Interrupt Controller (APIC)(D31:F0)................................433
13.5.1 APIC Register Map (LPC I/F—D31:F0)......................................................433
13.5.2 IND—Index Register (LPC I/F—D31:F0)...................................................434
13.5.3 DAT—Data Register (LPC I/F—D31:F0)....................................................434
13.5.4 EOIR—EOI Register (LPC I/F—D31:F0) ....................................................435
10
Datasheet
INTEL [ INTEL ]
