Intel® 82598 10 GbE Controller
Rev
Date
Comments
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Deleted "Pu" from LAN1_DIS_N and LAN0_DIS_N Type column in section 3.1.11.
Deleted "Pu" from the JTDI, JTMS, and JRST_N Type column in section 3.1.12.
Updated Table 3-2. Added pull-up and pull-down information for RMII_CRS_NV,
RMII_RXD[0], RMII_RXD[0], MDIO[0], MDIO[1], EE_CS_N, FLSH_CD_N, and JTCK.
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Added "470 ohm" to JRST_N coment columns in section 3.2.
Updated "Revision" paragraph on page 89. Replaced word 0x1D to offset 11 - Device
Revision ID.
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Updated "Memory Address Space" description on page 90. Replaced word 0x0F to
offset 7 - PCIe Control.
Updated section 4.1.9.3.3. Replaced words 0x24 and 0x14 with "at offset 7 - PCIe
Control".
Updated "Address" description on page 93. Replaced word 0x0F with "set by the
EEPROM at offset 7 (PCIe Control)".
Updated "Interrupt Pin" paragraph. Replaced words 0x24 and 0x14 with "at offset 1,
EEPROM Configuration Space 0/1,".
Updated section 4.2.1.3. Replaced "(in the LRXEN1) word to "at offset 31 - LAN 0
Receive Enable 1".
Updated "Vendor Specific ID" paragraph on page 133. Replaced "words 7.3.5.2 in" to
"at offset 1-3 (Ethernet Address)".
1.37
06/08
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Updated "CBDM" description on page 137. Replaced "words 0x0-0x2" with "at offset".
Updated paragraph on page 143 beginning with "Oplin responds to one of the
commands . . ".
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Updated section 6.2.4.2. Replaced "7.3.1.2 word" to "at address 0x00 (EEPROM
Control Word 1)".
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Updated second paragraph in section 6.2.5.1 beginning with "Enable Port 1/0 . . . ".
Updated third and fourth bullet in section 6.2.5.4.2 beginning with "as loaded from
the EEPROM . . . ".
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Deleted the RXE bit description from page 37.
Updated the "RST" bit description in Device Control Register table (bit 26).
Updated the Unlock_EEP bit description in the 9.2.3.4.16Firmware Semaphore
Register (bit 28).
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Updated sections 9.2.3.13.49 and 9.2.3.13.509. Included new RQSMR and TQSMR
descriptions.
Added "- (for both read and write-back formats)" to STA field description on page 69.
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Converted to single source using FrameMaker.
Updated internal/external pull-up/pull-down information.
2.0
2.2
12/08
February 2008
Initial Release (Intel Public).
Updated sections/figures/tables: Product Features, 1.9.9, 2.2, 2.3, 2.9, 2.13, Table 2-17,
3.1.1.6, Table 3-17, 3.1.1.14.4, Note after Table 3-25, Device Cap, Device Control, Device
Status, Link CAP Lin Control, Link Status, tables in section 3.1.1.14.6, 3.1.3.1, Figure 3-
10, 3.2.1.2, 3.2.1.3, Table 3-38, Table 3-39, 3.2.3.2.5, Figure 3-12, Figure 3-13,
3.3.2.3.1.7, Table 3-45, 3.4.3.1.1, 3.4.3.1.2, 3.4.3.4.2, 3.4.3.6.2, Figure 3-20, Figure 3-
21, Table 3-54, 3.5.2.4, 3.5.2.8, 3.5.2.10.1, 3.5.2.11, Table 3-59, Table 3-69, 3.5.3.3.2,
3.5.4.1, 3.5.4.2, Table 4-2, Table 4-4, 4.4.3.3.1 through 4.4.3.7, 4.4.3.3.12, 4.4.3.5.7
through 4.4.5.9, 4.4.3.6.2, 4.4.3.6.8, 4.4.3.6.11, 4.4.3.9, 4.4.3.11.1, 4.4.3.13.5,
4.4.3.13.8 through 4.4.3.13.10, 4.4.3.13.24, Table 5-7 through Table 5-10, Table 5-12,
and 5.6.4, 5.6.6.
2.3
May 2008
Replaced Large Send Offload (LSO) with TCP Segmentation Offload (TSO).
Removed all references to “Header Replication”.
Updated reference schematics.
Updated Tables: 2-12, 2-14, 2-16, 3-17, 3-58, 3-71, 4-4, 5-3 through 5-5, 5-12, 5-15, 5-
19,
2.4
August 2008
Updated Section: 1.2, 1.8, 1.9.10, 2.13, 3.1.1.10.1, 3.1.1.14.2, 3.2.2.14.3.1, 3.1.1.14.4,
3.1.4.3.4, 3.2.1.3, 3.3.1.3.2, 3.3.1.4.1, 3.3.1.4.4.2, 3.4 through 3.4.4, 3.5.2, 4.4.3.1.1,
4.4.3.3.7, 4.4.3.5.7, 4.4.3.6.4, 4.4.3.9.49, 4.4.3.9.50, 5.4.3, 5.5.1, 7.6, 7.8, 7.13.2.
Intel® 82598 10 GbE Controller
Datasheet
10
Reference Number: 319282-007
Revision Number: 3.2
October 2010
INTEL [ INTEL ]
