System Address Map
•
⎯
Device 2, Function 0
MMADR – IGD registers and internal graphics instruction port. (512 KB
window)
⎯
IOBAR – IO access window for internal graphics. Though this window
address/data register pair, using I/O semantics, the IGD and internal graphics
instruction port registers can be accessed. Note, this allows accessing the same
registers as MMADR. In addition, the IOBAR can be used to issue writes to the
GTTADR table.
⎯
⎯
GMADR – Internal graphics translation window (128 MB, 256 MB or 512 MB
window).
GTTADR – Internal graphics translation table location. (128 KB, 256 KB or
512 KB window).
•
⎯
Device 2, Function 1
MMADR – Function 1 IGD registers and internal graphics instruction port.
(512 KB window)
•
⎯
Device 3, Function 0:
MEHECIBAR – Function 0 HECI memory mapped registers (16B window)
The rules for the above programmable ranges are:
1. ALL of these ranges MUST be unique and NON-OVERLAPPING. It is the BIOS or
system designer’s responsibility to limit memory population so that adequate PCI,
PCI Express , High BIOS, PCI Express Memory Mapped space, and APIC memory
space can be allocated.
2. In the case of overlapping ranges with memory, the memory decode will be given
priority.
3. There are NO Hardware Interlocks to prevent problems in the case of overlapping
ranges.
4. Accesses to overlapped ranges may produce indeterminate results.
5. The only peer-to-peer cycles allowed below the top of Low Usable memory
(register TOLUD) are DMI Interface to PCI Express VGA range writes. Note that
peer to peer cycles to the Internal Graphics VGA range are not supported.
Datasheet
45
INTEL [ INTEL ]
