Land Listing and Signal Descriptions
Table 25.
Signal Description ( (Sheet 8 of 9))
Name
Type
Description
In the event of a catastrophic cooling failure, the processor will
automatically shut down when the silicon has reached a temperature
approximately 20 °C above the maximum TC. Assertion of
THERMTRIP# (Thermal Trip) indicates the processor junction
temperature has reached a level beyond where permanent silicon
damage may occur. Upon assertion of THERMTRIP#, the processor
will shut off its internal clocks (thus, halting program execution) in
an attempt to reduce the processor junction temperature. To protect
the processor, its core voltage (VCC) must be removed following the
THERMTRIP#
Output assertion of THERMTRIP#. Driving of the THERMTRIP# signal is
enabled within 10 μs of the assertion of PWRGOOD (provided VTT
and VCC are valid) and is disabled on de-assertion of PWRGOOD (if
V
TT or VCC are not valid, THERMTRIP# may also be disabled). Once
activated, THERMTRIP# remains latched until PWRGOOD, VTT, or
CC is de-asserted. While the de-assertion of the PWRGOOD, VTT, or
V
VCC will de-assert THERMTRIP#, if the processor’s junction
temperature remains at or above the trip level, THERMTRIP# will
again be asserted within 10 μs of the assertion of PWRGOOD
(provided VTT and VCC are valid).
TMS (Test Mode Select) is a JTAG specification support signal used
by debug tools.
TMS
Input
TRDY# (Target Ready) is asserted by the target to indicate that it is
TRDY#
TRST#
Input ready to receive a write or implicit writeback data transfer. TRDY#
must connect the appropriate pins/lands of all FSB agents.
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#
Input
must be driven low during power on Reset.
VCC are the power pins for the processor. The voltage supplied to
these pins is determined by the VID[6:0] pins.
VCC
Input
VCCPLL
Input VCCPLL provides isolated power for internal processor FSB PLLs.
VCC_SENSE is an isolated low impedance connection to processor
Output core power (VCC). It can be used to sense or measure voltage near
the silicon with little noise.
VCC_SENSE
This land is provided as a voltage regulator feedback sense point for
VCC_MB_
REGULATION
VCC. It is connected internally in the processor package to the sense
point land U27 as described in the Voltage Regulator-Down (VRD)
Output
11 Design Guide For Desktop and Transportable LGA775 Socket.
VID[6:1] (Voltage ID) signals are used to support automatic
selection of power supply voltages (VCC). Refer to the appropriate
platform design guide or the Voltage Regulator-Down (VRD) 11
Design Guide For Desktop and Transportable LGA775 Socket for
more information. The voltage supply for these signals must be valid
VID[6:1]
Output before the VR can supply VCC to the processor. Conversely, the VR
output must be disabled until the voltage supply for the VID signals
becomes valid. The VID signals are needed to support the processor
voltage specification variations. See Table 2 for definitions of these
signals. The VR must supply the voltage that is requested by the
signals, or disable itself.
This land is tied high on the processor package and is used by the
VR to choose the proper VID table. Refer to the Voltage Regulator-
Down (VRD) 11 Design Guide For Desktop and Transportable
VID_SELECT
Output
LGA775 Socket for more information.
Datasheet
73
INTEL [ INTEL ]
