Registers
14.3.3
Error Registers
14.3.3.1
EMASK: Error Mask
This register masks errors in the FERR and NERR registers as well as disabling some
types of error detection. A ‘0’ in any field enables that error. A ‘1’ in any field masks
(disables) that error. Multiple bits can be set in this register. An enabled error sets
error status, updates error logs, and generates link signals. A masked error does not
affect error status, error logs, or link signals.
Device:
NodeID
Function: 1
Offset:
Bit
8Ch
Attr
Default
Description
31:8
RV
0
1
1
1
Reserved
Reserved
Reserved
7
6
5
RWST
RWST
RWST
INJERR: Error Injection has sourced an injected error bit in the status
return field (optional)
4
3
RWST
RWST
1
0
INJALERT: Error Injection has sourced an injected alert error (optional)
FEWEDGES: tClk Training Violation (no sync cmd for 2x SYNCTRAININT -
typically 84 frames)
2
1
0
RWST
RWST
RWST
1
1
0
OVERTEMP: Temp > TEMPHI and temp enabled
UNIMPLCFG: Unimplemented Configuration Address
CMDCRCERR: SB CRC Error
14.3.3.2
FERR: First Error
This register contains bits specifying which errors occurred first as related to the FBD
channel.
Device:
NodeID
Function: 1
Offset:
Bit
90h
Attr
Default
Description
31:8
RV
0
Reserved
7
RWCST
0
WBUFOVFL: Write Buffer overflow
- Implementation Specific - only supported for debug
6
5
RWCST
RWCST
0
0
WPLDERR: Wrong Number of Write Payloads (Buffer Underflow)
- Implementation Specific - only supported for debug
INJERR: Error Injection has sourced an injected error bit in the status
return field (optional)
4
3
RWCST
RWCST
0
0
INJALERT: Error Injection has sourced an injected alert error (optional)
FEWEDGES: tClk Training Violation (no sync cmd for2x SYNCTRAININT -
typically 84 frames)
Logs in RECFBD registers. Sends Alerts NB. Triggers auto self refresh SM.
2
1
RWCST
RWCST
0
0
OVERTEMP: Temp > TEMPHI and temp enabled
Fatal. AMB shuts down.
UNIMPLCFG: Unimplemented Configuration Address
Correctable. Logs in RECCFG* registers. AMB drops the command.
Intel® 6400/6402 Advanced Memory Buffer Datasheet
181
INTEL [ INTEL ]
