Signal Lists
Table 13-3. Pin Description (Sheet 2 of 2)
Signal
Type
Description
ODT0A, ODT0B
CLK[3:0]
O
O
DIMM On-Die-Termination: Dynamic ODT enables for each DIMM on the channel.
Clock: Clocks to DRAMs. CLK0 and CLK1 are always used. CLK2 and CLK3 are optional and
may be disabled when not required.
CLK[3:0]
O
Clock Complement: Clocks to DRAMs.
DDR Compensation
DDRC_C14
DDRC_B18
DDRC_C18
DDRC_B12
DDRC_C12
Clocking
A
A
A
A
A
DDR Compensation Common: Common return (ground) pin for DDRC_B18 and DDRC_C18
DDR Compensation Ball Resistor connected to Compensation Common above
DDR Compensation Ball Resistor connected to Compensation Common above
DDR Compensation Ball Resistor connected to VSS
DDR Compensation Ball Resistor connected to VDD
SCK
I
I
AMB Clock: This is one of the two differential reference clock inputs to the Phase Locked Loop
in the AMB core. Phase Locked Loops in the AMB will shift this to all frequencies required by
the core, DDR channels, and FBD Channel.
SCK
AMB Clock Complement: This is the other differential reference clock input to the Phase
Locked Loop in the AMB core. Phase Locked Loops in the AMB will shift this to all frequencies
required by the core, DDR channels, and FBD Channel.
VCCAPLL
A
A
VCC: PLL Analog Voltage for the core PLL (See Chapter 8, Clocking)
VSS: PLL Analog Voltage for the core PLL (See Chapter 8, Clocking)
VSSAPLL
System Management
SCL
I/O
I/O
SMBus Clock
SDA
SMBus Address/Data
DIMM Select ID
SA[2:0]
Reset
RESET#
Power Good Reset
Miscellaneous Test
TEST (6 pins)
TESTLO (3 pins)
TESTLO_AB20
NC
A
Pin for debug and test. Must be floated on DIMM.
Pin for debug and test. Must be tied to Ground on DIMM
A
Pin for debug and test. Connected to two resistors. One resistor is connected to VCCFBD,
the other resistor is connected to VSS.
TESTLO_AC20
A
Pin for debug and test. Connected to two resistors. One resistor is connected to VCCFBD,
the other resistor is connected to VSS.
Power Supplies
VCC (2pins)
VCCFBD (8 pins)
VDD (24 pins)
VSS (156 pins)
VDDSPD
A
A
A
A
A
1.5V nominal supply for core logic
1.5V nominal supply for FBD high speed I/O
1.8V nominal supply for DDR I/O
Ground
3.3V nominal supply for SMB receivers and ESD diodes
Other Pins
BFUNC
I
Buffer Function Bit: When BFUNC = 0, AMB is used as a regular buffer on FB-DIMM. When
BFUNC = 1, AMB is used as either a repeater or a buffer for LAI function. On FB-DIMM, BFUNC
is tied to Ground
“a”
RFU (18 pins)
NC
Reserved for Future Use. Must be floated on DIMM. RFU pins denoted by
for forwarded clocks in future AMB implementations.
are reserved
Other No Connect Pins
NC (129 pins)
NC
No Connect pins
Intel® 6400/6402 Advanced Memory Buffer Datasheet
157
INTEL [ INTEL ]
