Signal Lists
Table 13-2. Buffer Signal Types
Buffer
Direction
Description
I
Input signal
O
Output signal
Analog
A
I/O
Bidirectional (input/output) signal
13.2
Intel 6400/6402 Advanced Memory Buffer (AMB)
Pin Description List
Table 13-3 describes the Intel 6400/6402 Advanced Memory Buffer (AMB)
packagepins.
Table 13-3. Pin Description (Sheet 1 of 2)
Signal
Type
Description
Channel Interface
PN[13:0]
O
Northbound Output Data: High speed serial signal. Read path from AMB toward host on
primary side of the DIMM connector.
PN[13:0]
SN[13:0]
O
I
Northbound Output Data Complement
Northbound Input Data: High speed serial signal. Read path from the previous AMB toward
this AMB on secondary side of the DIMM connector.
SN[13:0]
PS[9:0]
I
I
Northbound Input Data Complement
Southbound Input Data: High speed serial signal. Write path from host toward AMB on
primary side of the DIMM connector.
PS[9:0]
SS[9:0]
I
Southbound Input Data Complement
O
Southbound Output Data: High speed serial signal. Write path from this AMB toward next
AMB on secondary side of the DIMM connector. These output buffers are disabled for the last
AMB on the channel.
SS[9:0]
FBDRES
O
A
Southbound Output Data Complement
External precision resistor connected to VCC. On-die termination calibrated against this
resistor.
DRAM Interface
CB[7:0]
I/O
I/O
I/O
I/O
O
Check bits
DQ[63:0]
Data
DQS[17:0]
DQS[17:0]
Data Strobe: DDR2 data and check-bit strobe.
Data Strobe Complement: DDR2 data and check-bit strobe complements.
Address: Used for providing multiplexed row and column address to SDRAM.
A0A-A15A,
A0B-A15B
BA0A-BA2A,
BA0B-BA2B
O
Bank Active: Used to select the bank within a rank.
RASA, RASB
CASA, CASB
WEA, WEB
O
O
O
O
Row Address Strobe: Used with CS, CAS, and WE to specify the SDRAM command.
Column Address Strobe: Used with CS, RAS, and WE to specify the SDRAM command.
Write Enable: Used with CS, CAS, and RAS to specify the SDRAM command.
CS0A-CS1A,
CS0B-CS1B
Chip Select: Used with CAS, RAS, and WE to specify the SDRAM command. These signals are
used for selecting one of two SDRAM ranks. CS0 is used to select the first rank and CS1 is
used to select the second rank.
CKE0A-CKE1A,
CKE0B-CKE1B
O
Clock Enable: DIMM command register enable.
156
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
