DDR MemBIST
11.5.2
MB Flow Control State Machine
Figure 11-7. MBFSM Diagram
core_rst_l =0
MemBist MBFSM
IDLE
mbstart &
(wronly |
wrrdcmp)
RD_DONE
Always
rdidle & ~rd2wr
or
lfsrdata
WR_START
wridle & rd2wr
cget &
lastaddr &
rd2wr
WR_SEED
RD_WAIT
RD_WRAVL
~ lfsrdata
cget & lastaddr & ~rdw2wr
Always
lfsrseed_done
WR_NXTAD
wronly
RD_AVAIL
cget & rd2wr
RD_NXTWR
cget & ~lastaddr
Always
cget &
~lastaddr &
rd2wr
Always
cget &
~lastaddr &
~rd2wr
WR_AVAIL
cget & lastaddr
WR_WAIT
RD_NXTAD
lfsrseed_done
~ lfsrdata
RD_SEED
writeidle
lfsrdata
WR_DONE
~wronly
RD_START
This FSM controls the MemBIST flow and generates read/write commands for
MemBIST.
• When MBCSR bit[31] is programmed to begin execution, the MemBIST FSM will
transition out of the IDLE state to either WR_START or RD_START, depending upon
the MemBIST command programmed in MBCSR:cmd.
• In WR_START state, FSM will look at the decoding of DATA type selection. If LFSR
data type generation is selected, FSM will go to WR_SEED state. If not, FSM will
directly go to WR_NXTAD state.
Intel® 6400/6402 Advanced Memory Buffer Datasheet
139
INTEL [ INTEL ]
