Electrical Specifications
Table 2-7 outlines the signals which include on-die termination (RTT). Open drain
signals are also included. Table 2-8 provides signal reference voltages.
Table 2-7.
Signal Description Table
Signals with R
Signals with no R
TT
TT
A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#, A20M#, BCLK[1:0], BPM[5:0]#, BR[1:0]#, BSEL[2:0],
BNR#, BPRI#, COMP[7:4], D[63:0]#, DBI[3:0]#, COMP[3:0], FERR#/PBE#, GTLREF_ADD_C[1:0],
DBSY#, DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#, GTLREF_DATA_C[1:0], IERR#, IGNNE#, INIT#, LINT0/
DSTBP[3:0]#, FORCEPR#, HIT#, HITM#, LOCK#,
MCERR#, PROCHOT#, REQ[4:0]#, RS[2:0]#,
INTR, LINT1/NMI, LL_ID[1:0], MS_ID[1:0], PWRGOOD,
RESET#, SKTOCC#, SMI#, STPCLK#, TDO,
TESTHI[11:0], THERMDA, THERMDA2, THERMDC,
THERMDC2, THERMTRIP#, VCC_DIE_SENSE,
VCC_DIE_SENSE2, VID[5:0], VID_SELECT,
2
2
2
RSP#, TCK , TDI , TEST_BUS, TMS , TRDY#,
2
TRST#
VSS_DIE_SENSE, VSS_DIE_SENSE2, VTTPWRGD
1
Open Drain Signals
BPM[5:0]#, BR0#, FERR#/PBE#, IERR#, PROCHOT#, TDO, THERMTRIP#
Notes:
1.
2.
Signals that do not have R , nor are actively driven to their high voltage level.
TT
The on-die termination for these signals is not R . TCK, TDI, and TMS have an approximately 150 KΩ
TT
pullup to V .
TT
Table 2-8.
Signal Reference Voltages
GTLREF
VTT / 2
1
A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#, A20M#, IGNNE#, INIT#, PWRGOOD , SMI#, STPCLK#,
1
1
1
1
BNR#, BPM[5:0]#, BPRI#, BR[1:0]#, D[63:0]#,
DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#, DRDY#,
TCK , TDI , TMS , TRST# , VTTPWRGD
2
DSTBN[3:0]#, DSTBP[3:0]#, FORCEPR# , HIT#,
HITM#, IERR#, LINT0/INTR, LINT1/NMI, LOCK#,
MCERR#, RESET#, REQ[4:0]#, RS[2:0]#, RSP#,
TRDY#
Notes:
1.
2.
These signals also have hysteresis added to the reference voltage. See Table 2-14 for more information.
Use Table 2-15 for signal FORCEPR# specifications.
2.8
GTL+ Asynchronous and AGTL+ Asynchronous
Signals
Input signals such as A20M#, FORCEPR#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI,
SMI# and STPCLK# utilize GTL+ input buffers. Legacy output FERR#/PBE# and other
non-AGTL+ signals IERR#, THERMTRIP# and PROCHOT# utilize GTL+ output buffers.
All of these asynchronous GTL+ signals follow the same DC requirements as AGTL+
signals; however, the outputs are not driven high (during the electrical 0-to-1
transition) by the processor. FERR#/PBE#, IERR#, and IGNNE# have now been defined
as AGTL+ asynchronous signals as they include an active p-MOS device. Asynchronous
GTL+ and asynchronous AGTL+ signals do not have setup or hold time specifications in
relation to BCLK[1:0]; however, all of the asynchronous GTL+ and asynchronous
AGTL+ signals are required to be asserted/deasserted for at least six BCLKs in order for
the processor to recognize them. See Table 2-15 for the DC specifications for the
asynchronous GTL+ signal groups.
2.9
Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP)
logic, it is recommended that the processor(s) be first in the TAP chain and followed by
any other components within the system. A translation buffer should be used to
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
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