Electrical Specifications
2.5
Voltage Identification (VID)
The Voltage Identification (VID) specification for the Dual-Core Intel Xeon Processor
5000 series set by the VID signals is the reference VR output voltage to be delivered to
the processor Vcc pins. VID signals are open drain outputs, which must be pulled up to
VTT. Please refer to Table 2-12 for the DC specifications for these signals. A minimum
voltage is provided in Table 2-10 and changes with frequency. This allows processors
running at a higher frequency to have a relaxed minimum voltage specification. The
specifications have been set such that one voltage regulator can operate with all
supported frequencies.
Individual processor VID values may be calibrated during manufacturing such that two
devices at the same core frequency may have different default VID settings. This is
reflected by the VID range values provided in Table 2-3.
The Dual-Core Intel Xeon Processor 5000 series use six voltage identification signals,
VID[5:0], to support automatic selection of power supply voltages. The processor uses
the VTTPWRGD input to determine that the supply voltage for VID[5:0] is stable and
within specification.Table 2-3 specifies the voltage level corresponding to the state of
VID[5:0]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to a low
voltage level. The definition provided in Table 2-3 is not related in any way to previous
Intel® Xeon® processors or voltage regulator designs. If the processor socket is empty
(VID[5:0] = x11111), or the voltage regulation circuit cannot supply the voltage that is
requested, it must disable itself.
The Dual-Core Intel Xeon Processor 5000 series provide the ability to operate while
transitioning to an adjacent VID and its associated processor core voltage (VCC). This
will represent a DC shift in the load line. It should be noted that a low-to-high or high-
to-low voltage state change may result in as many VID transitions as necessary to
reach the target core voltage. Transitions above the specified VID are not permitted.
Table 2-10 includes VID step sizes and DC shift ranges. Minimum and maximum
voltages must be maintained as shown in Table 2-11 and Figure 2-4.
The VRM or EVRD utilized must be capable of regulating its output to the value defined
by the new VID. DC specifications for dynamic VID transitions are included in
Table 2-10 and Table 2-11.
Power source characteristics must be guaranteed to be stable whenever the supply to
the voltage regulator is stable.
Table 2-3.
Voltage Identification Definition (Sheet 1 of 2)
VID4 VID3 VID2 VID1 VID0 VID5 VCC_MAX
VID4 VID3 VID2 VID1 VID0 VID5 VCC_MAX
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0.8375
0.8500
0.8625
0.8750
0.8875
0.9000
0.9125
0.9250
0.9375
0.9500
0.9625
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1.2125
1.2250
1.2375
1.2500
1.2625
1.2750
1.2875
1.3000
1.3125
1.3250
1.3375
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
19
INTEL [ INTEL ]
