Introduction
and can thus help improve the overall security of the system. For further information on
Execute Disable Bit functionality see http://www.intel.com/cd/ids/developer/asmo-na/
eng/149308.htm.
The Dual-Core Intel Xeon Processor 5000 series support Intel® Virtualization
Technology, virtualization within the processor. Intel Virtualization Technology is a set of
hardware enhancements that can improve virtualization solutions. Intel Virtualization
Technology is used in conjunction with Virtual Machine Monitor software enabling
multiple, independent software environments inside a single platform. More
information on Intel Virtualization Technology can be found at http://www.intel.com/
technology/computing/vptech/index.htm.
The Dual-Core Intel Xeon Processor 5000 series are intended for high performance
workstation and server systems. The Dual-Core Intel Xeon Processor 5063 is a lower
power version of the Dual-Core Intel Xeon Processor 5000 series. The Dual-Core Intel
Xeon Processor 5000 series support a new Dual Independent Bus (DIB) architecture
with one processor socket on each bus, up to two processor sockets in a system. The
DIB architecture provides improved performance by allowing increased FSB speeds and
bandwidth. The Dual-Core Intel Xeon Processor 5000 series will be packaged in an FC-
LGA6 Land Grid Array package with 771 lands for improved power delivery. It utilizes a
surface mount LGA771 socket that supports Direct Socket Loading (DSL).
Table 1-1.
Dual-Core Intel® Xeon® Processor 5000 Series Features
# Cores Per
Package
L2 Advanced
Transfer Cache
Hyper-Threading
Technology
Front Side Bus
Frequency
Package
1
2
2 MB per core
4 MB total
Yes
667 MHz
1066 MHz
FC-LGA6
771 Lands
Notes:
1. Total accessible size of L2 caches may vary by one cache line pair (128 bytes) per core, depending on usage
and operating environment.
The Dual-Core Intel Xeon Processor 5000 series-based platforms implement
independent core voltage (VCC) power planes for each processor. FSB termination
voltage (VTT) is shared and must connect to all FSB agents. The processor core voltage
utilizes power delivery guidelines specified by VRM/EVRD 11.0 and its associated load
line. Refer to the appropriate platform design guidelines for implementation details.
The Dual-Core Intel Xeon Processor 5000 series support a 1066/667 MHz Front Side
Bus frequency. The FSB utilizes a split-transaction, deferred reply protocol and Source-
Synchronous Transfer (SST) of address and data to improve performance. The
processor transfers data four times per bus clock (4X data transfer rate, as in AGP 4X).
Along with the 4X data bus, the address bus can deliver addresses two times per bus
clock and is referred to as a ‘double-clocked’ or a 2X address bus. In addition, the
Request Phase completes in one clock cycle. Working together, the 4X data bus and 2X
address bus provide a data bus bandwidth of up to 8.5 GBytes/second. (5.3 GBytes/
second for Dual-Core Intel Xeon Processor 5000 series 667) Finally, the FSB is also
used to deliver interrupts.
Signals on the FSB use Assisted Gunning Transceiver Logic (AGTL+) level voltages.
Section 2.1 contains the electrical specifications of the FSB while implementation
details are fully described in the appropriate platform design guidelines (refer to
Section 1.3).
10
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
INTEL [ INTEL ]
