1-Gbit P30 Family
7.3
AC Read Specifications
Table 16.
AC Read Specifications for 64/128-Mbit Densities (Sheet 1 of 2)
Num
Symbol
Parameter
Min
Max
Unit
Notes
Asynchronous Specifications
R1
R2
tAVAV
tAVQV
tELQV
Read cycle time
85
-
-
85
85
25
150
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address to output valid
CE# low to output valid
OE# low to output valid
RST# high to output valid
CE# low to output in low-Z
OE# low to output in low-Z
CE# high to output in high-Z
OE# high to output in high-Z
R3
-
R4
-
1,2
1
tGLQV
tPHQV
tELQX
tGLQX
tEHQZ
tGHQZ
tOH
R5
-
R6
0
0
-
1,3
1,2,3
R7
-
R8
24
24
-
R9
-
1,3
R10
R11
R12
R13
R15
R16
R17
Output hold from first occurring address, CE#, or OE# change
CE# pulse width high
0
20
-
tEHEL
tELTV
tEHTZ
tGLTV
tGLTX
tGHTZ
-
1
CE# low to WAIT valid
17
20
17
-
CE# high to WAIT high-Z
-
1,3
1
OE# low to WAIT valid
-
OE# low to WAIT in low-Z
0
-
1,3
OE# high to WAIT in high-Z
20
Latching Specifications
R101
R102
R103
R104
R105
R106
R108
R111
tAVVH
tELVH
tVLQV
tVLVH
tVHVL
tVHAX
tAPA
Address setup to ADV# high
CE# low to ADV# high
ADV# low to output valid
ADV# pulse width low
10
10
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
85
-
1
10
10
9
ADV# pulse width high
Address hold from ADV# high
Page address access
-
-
1,4
1
-
25
-
tphvh
RST# high to ADV# high
30
Clock Specifications
R200
R201
R202
R203
fCLK
tCLK
CLK frequency
CLK period
-
25
5
40
-
MHz
ns
1,3,6
tCH/CL
CLK high/low time
CLK fall/rise time
-
ns
tFCLK/RCLK
-
3
ns
Synchronous Specifications
R301
R302
R303
R304
tAVCH/L
tVLCH/L
Address setup to CLK
ADV# low setup to CLK
CE# low setup to CLK
CLK to output valid
9
9
9
-
-
-
ns
ns
ns
ns
1
tELCH/L
-
t
CHQV / tCLQV
20
Datasheet
Intel StrataFlash® Embedded Memory (P30)
Order Number: 306666, Revision: 001
April 2005
35
INTEL [ INTEL ]
