28F128 (INTEL) PDF技术资料下载 28F128 供应信息 IC Datasheet 数据表 (6/58 页)-芯三七

28F128J3A, 28F640J3A, 28F320J3A

1.0

Product Overview

The 0.25 µ 3 Volt Intel StrataFlash memory family contains high-density memories organized as

16 Mbytes or 8 Mwords (128-Mbit), 8 Mbytes or 4 Mwords (64-Mbit), and 4 Mbytes or 2 Mwords

(32-Mbit). These devices can be accessed as 8- or 16-bit words. The 128-Mbit device is organized

as one-hundred-twenty-eight 128-Kbyte (131,072 bytes) erase blocks. The 64-Mbit device is

organized as sixty-four 128-Kbyte erase blocks while the 32-Mbits device contains thirty-two

128-Kbyte erase blocks. Blocks are selectively and individually lockable and unlockable in-

system. A 128-bit protection register has multiple uses, including unique flash device

identification.

The device’s optimized architecture and interface dramatically increases read performance by

supporting page-mode reads. This read mode is ideal for non-clock memory systems.

A Common Flash Interface (CFI) permits software algorithms to be used for entire families of

devices. This allows device-independent, JEDEC ID-independent, and forward- and backward-

compatible software support for the specified flash device families. Flash vendors can standardize

their existing interfaces for long-term compatibility.

Scalable Command Set (SCS) allows a single, simple software driver in all host systems to work

with all SCS-compliant flash memory devices, independent of system-level packaging (e.g.,

memory card, SIMM, or direct-to-board placement). Additionally, SCS provides the highest

system/device data transfer rates and minimizes device and system-level implementation costs.

A Command User Interface (CUI) serves as the interface between the system processor and

internal operation of the device. A valid command sequence written to the CUI initiates device

automation. An internal Write State Machine (WSM) automatically executes the algorithms and

timings necessary for block erase, program, and lock-bit configuration operations.

A block erase operation erases one of the device’s 128-Kbyte blocks typically within one second—

independent of other blocks. Each block can be independently erased 100,000 times. Block erase

suspend mode allows system software to suspend block erase to read or program data from any

other block. Similarly, program suspend allows system software to suspend programming (byte/

word program and write-to-buffer operations) to read data or execute code from any other block

that is not being suspended.

Each device incorporates a Write Buffer of 32 bytes (16 words) to allow optimum programming

performance. By using the Write Buffer, data is programmed in buffer increments. This feature can

improve system program performance more than 20 times over non-Write Buffer writes.

Individual block locking uses block lock-bits to lock and unlock blocks. Block lock-bits gate block

erase and program operations. Lock-bit configuration operations set and clear lock-bits (Set Block

Lock-Bit and Clear Block Lock-Bits commands).

The status register indicates when the WSM’s block erase, program, or lock-bit configuration

operation is finished.

The STS (STATUS) output gives an additional indicator of WSM activity by providing both a

hardware signal of status (versus software polling) and status masking (interrupt masking for

background block erase, for example). Status indication using STS minimizes both CPU overhead

and system power consumption. When configured in level mode (default mode), it acts as a RY/

BY# pin. When low, STS indicates that the WSM is performing a block erase, program, or lock-bit

configuration. STS-high indicates that the WSM is ready for a new command, block erase is

Preliminary

1

28F128J3A, 28F640J3A, 28F320J3A

suspended (and programming is inactive), program is suspended, or the device is in reset/power-

down mode. Additionally, the configuration command allows the STS pin to be configured to pulse

on completion of programming and/or block erases.

Three CE pins are used to enable and disable the device. A unique CE logic design (see Table 2,

“Chip Enable Truth Table” on page 7) reduces decoder logic typically required for multi-chip

designs. External logic is not required when designing a single chip, a dual chip, or a 4-chip

miniature card or SIMM module.

The BYTE# pin allows either x8 or x16 read/writes to the device. BYTE# at logic low selects 8-bit

mode; address A₀selects between the low byte and high byte. BYTE# at logic high enables 16-bit

operation; address A₁becomes the lowest order address and address A₀is not used (don’t care). A

device block diagram is shown in Figure 1 on page 2.

When the device is disabled (see Table 2 on page 7) and the RP# pin is at V_CC, the standby mode is

enabled. When the RP# pin is at GND, a further power-down mode is enabled which minimizes

power consumption and provides write protection during reset. A reset time (t_PHQV) is required

from RP# switching high until outputs are valid. Likewise, the device has a wake time (t_PHWL

)

from RP#-high until writes to the CUI are recognized. With RP# at GND, the WSM is reset and the

status register is cleared.

3 Volt Intel StrataFlash memory devices are available in two package types. Both 56-lead TSOP

(Thin Small Outline Package) and BGA (Ball Grid Array Package) support all offered densities.

Figure 2 and Figure 3 show the pinouts.

Figure 1. 3 Volt Intel^®StrataFlash™ Memory Block Diagram

DQ₀- DQ₁₅

Output

Buffer

V_CCQ

Input Buffer

V_CC

BYTE#

Query

I/O Logic

CE₀

CE₁

CE₂

WE#

OE#

RP#

Identifier

Register

CE

Logic

Command

User

Interface

Status

Register

Multiplexer

A₀- A₂

Data

Comparator

32-Mbit: A₀- A₂₁

64-Mbit: A₀- A₂₂

128-Mbit: A₀- A₂₃

Y-Decoder

X-Decoder

Y-Gating

STS

Input Buffer

Write State

Machine

Program/Erase

Voltage Switch

V_PEN

32-Mbit: Thirty-two

64-Mbit: Sixty-four

128-Mbit: One-hundred

twenty-eight

Address

Latch

V_CC

GND

128-Kbyte Blocks

Address

Counter

2

Preliminary

28F128J3A, 28F640J3A, 28F320J3A

Table 1. Lead Descriptions

Symbol

Type

Name and Function

BYTE-SELECT ADDRESS: Selects between high and low byte when the device is in x8 mode. This

A

INPUT

address is latched during a x8 program cycle. Not used in x16 mode (i.e., the A input buffer is turned

0

off when BYTE# is high).

ADDRESS INPUTS: Inputs for addresses during read and program operations. Addresses are

internally latched during a program cycle.

A –A

INPUT

32-Mbit: A –A

1

23

0

21

22

64-Mbit: A –A

0

128-Mbit: A –A

0

23

LOW-BYTE DATA BUS: Inputs data during buffer writes and programming, and inputs commands

during Command User Interface (CUI) writes. Outputs array, query, identifier, or status data in the

appropriate read mode. Floated when the chip is de-selected or the outputs are disabled. Outputs

INPUT/

OUTPUT

DQ –DQ

0

7

DQ –DQ are also floated when the Write State Machine (WSM) is busy. Check SR.7 (status register

6

0

bit 7) to determine WSM status.

HIGH-BYTE DATA BUS: Inputs data during x16 buffer writes and programming operations. Outputs

array, query, or identifier data in the appropriate read mode; not used for status register reads. Floated

when the chip is de-selected, the outputs are disabled, or the WSM is busy.

DQ –

INPUT/

OUTPUT

8

DQ

15

CHIP ENABLES: Activates the device’s control logic, input buffers, decoders, and sense amplifiers.

When the device is de-selected (see Table 2 on page 7), power reduces to standby levels.

CE ,

0

CE ,

INPUT

All timing specifications are the same for these three signals. Device selection occurs with the first

edge of CE , CE , or CE that enables the device. Device deselection occurs with the first edge of

1

CE

2

0

1

2

CE , CE , or CE that disables the device (see Table 2 on page 7).

0

1

2

RESET/ POWER-DOWN: Resets internal automation and puts the device in power-down mode. RP#-

high enables normal operation. Exit from reset sets the device to read array mode. When driven low,

RP# inhibits write operations which provides data protection during power transitions.

RP#

OUTPUT ENABLE: Activates the device’s outputs through the data buffers during a read cycle. OE# is

active low.

OE#

WE#

INPUT

WRITE ENABLE: Controls writes to the Command User Interface, the Write Buffer, and array blocks.

WE# is active low. Addresses and data are latched on the rising edge of the WE# pulse.

STATUS: Indicates the status of the internal state machine. When configured in level mode (default

mode), it acts as a RY/BY# pin. When configured in one of its pulse modes, it can pulse to indicate

program and/or erase completion. For alternate configurations of the STATUS pin, see the

OPEN

DRAIN

OUTPUT

STS

Configurations command. Tie STS to V

with a pull-up resistor.

CCQ

BYTE ENABLE: BYTE# low places the device in x8 mode. All data is then input or output on DQ –

0

DQ , while DQ –DQ float. Address A selects between the high and low byte. BYTE# high places

7

8

15

0

BYTE#

INPUT

the device in x16 mode, and turns off the A input buffer. Address A then becomes the lowest order

0

1

address.

ERASE / PROGRAM / BLOCK LOCK ENABLE: For erasing array blocks, programming data, or

configuring lock-bits.

V

PEN

With V

≤ V

, memory contents cannot be altered.

PEN

PENLK

V

SUPPLY DEVICE POWER SUPPLY: With V ≤ V

, all write attempts to the flash memory are inhibited.

LKO

CC

OUTPUT

OUTPUT BUFFER POWER SUPPLY: This voltage controls the device’s output voltages. To obtain

output voltages compatible with system data bus voltages, connect V to the system supply voltage.

BUFFER

SUPPLY

CCQ

GND

NC

SUPPLY GROUND: Do not float any ground pins.

NO CONNECT: Lead is not internally connected; it may be driven or floated.

DON’T USE: Do not drive ball to V or V , leave disconnected

DU

IH

IL

Preliminary

3

28F128J3A, 28F640J3A, 28F320J3A

Figure 2. 3 Volt Intel^®StrataFlash™ Memory Easy BGA Package

1

2

3

4

5

6

7

8

7

6

5

4

3

2

1

A

B

C

A

B

C

(1)

A₁

A₆

A₈V_PENA₁₃V_CCA₁₈A₂₂

A₂₂

A₁₈V_CCA₁₃V_PENA₈

A₆

A₁

A₂GND A₉CE₀# A₁₄

DU

A₁₉CE₁#

CE₁# A₁₉

DU

A₁₄CE₀# A₉GND A₂

A₃

A₄

A₇

A₅

A₁₀

A₁₂

A₁₅

A₂₀

A₂₁

A₁₇

A₂₀

A₁₅

A₁₂

A₁₀

A₇

A₅

A₃

A₄

D

A₁₁RP# DU DU

A₁₆A₁₇

A₁₆DU DU RP# A₁₁

E

F

E

F

DQ₈DQ₁DQ₉DQ₃DQ₄DU DQ₁₅STS

STS DQ₁₅DU DQ₄DQ₃DQ₉DQ₁DQ₈

OE# DU DU DQ₁₂DQ₁₁DQ₁₀DQ₀BYTE#

BYTE# DQ₀DQ₁₀DQ₁₁DQ₁₂DU DU OE#

G

H

(2)

A₂₃

A₀DQ₂V_CCQDQ₅DQ₆DQ₁₄WE#

WE# DQ₁₄DQ₆DQ₅V_CCQDQ₂A₀A₂₃

H

(3)

CE₂# DU V_CCGND DQ₁₃GND DQ₇A₂₄

A₂₄

DQ₇GND DQ₁₃GND V_CCDU CE₂#

Top View - Ball Side Down

Bottom View - Ball Side Up

32 Mbit, 64 Mbit and 128 Mbit: 10 x 13 x 1.2 mm

1.0 mm-ball pitch

0667-02

NOTES:

1. Address A is only valid on 64-Mbit densities and above, otherwise, it is a no connect (NC)

22

2. Address A is only valid on 128-Mbit densities and above, otherwise, it is a no connect (NC)

23

3. Address A is only valid on 256-Mbit densities and above, otherwise, it is a no connect (NC)

24

4. Don’t Use (DU) pins refer to pins that should not be connected

4

Preliminary

28F128J3A, 28F640J3A, 28F320J3A

Figure 3. 3 Volt Intel^®StrataFlash™ Memory 56-Lead TSOP (32/64/128 Mbit) Offers an Easy

Migration from the 32-Mbit Intel StrataFlash Component (28F320J5) or the 16-Mbit

FlashFile™ Component (28F160S3)

3 Volt Intel

StrataFlash

Memory

3 Volt Intel

StrataFlash

Memory

28F160S3 28F320J5

28F320J5 28F160S3

32/64/128M

(1)

(3)

NC

CE₁

A₂₁

A₂₀

A₁₉

A₁₈

A₁₇

A₂₂

1

2

3

4

5

6

7

8

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

A₂₄

NC

CE₁

NC

A₂₀

A₁₉

A₁₈

A₁₇

A₁₆

V_CC

A₁₅

A₁₄

A₁₃

A₁₂

CE₀

V_PP

RP#

A₁₁

A₁₀

A₉

A₈

GND

A₇

A₆

A₅

A₄

A₃

A₂

A₁

WP#

CE₁

A₂₁

A₂₀

A₁₉

A₁₈

A₁₇

A₁₆

V_CC

A₁₅

A₁₄

A₁₃

A₁₂

CE₀

V_PEN

RP#

A₁₁

A₁₀

A₉

A₈

GND

A₇

A₆

A₅

A₄

A₃

A₂

A₁

WE#

OE#

STS

DQ₁₅

DQ₇

DQ₁₄

DQ₆

GND

DQ₁₃

DQ₅

DQ₁₂

DQ₄

V_CCQ

GND

DQ₁₁

DQ₃

DQ₁₀

DQ₂

V_CC

WE#

OE#

STS

DQ₁₅

DQ₇

DQ₁₄

DQ₆

GND

DQ₁₃

DQ₅

DQ₁₂

DQ₄

V_CCQ

GND

DQ₁₁

DQ₃

DQ₁₀

DQ₂

WE#

OE#

STS

DQ₁₅

DQ₇

DQ₁₄

DQ₆

GND

DQ₁₃

DQ₅

DQ₁₂

DQ₄

V_CC

GND

DQ₁₁

DQ₃

DQ₁₀

DQ₂

V_CC

DQ₉

DQ₁

DQ₈

DQ₀

A₀

BYTE#

NC

A₁₆

(4)

V_CC

9

A₁₅

A₁₄

A₁₃

A₁₂

CE₀

V_PEN

RP#

A₁₁

A₁₀

A₉

A₈

GND

A₇

A₆

A₅

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

Intel^®StrataFlash™ Memory

56-Lead TSOP

Standard Pinout

14 mm x 20 mm

Top View

(4)

V_CC

DQ₉

DQ₁

DQ₈

DQ₀

A₀

DQ₉

DQ₁

DQ₈

DQ₀

A₀

BYTE#

NC

CE₂

A₄

A₃

A₂

A₁

BYTE#

(2)

A₂₃

CE₂

Highlights pinout changes

0667-03

NOTES:

1. A exists on 64-, 128- and 256-Mbit densities. On 32-Mbit densities this pin is a no-connect (NC).

22

2. A exists on 128-Mbit densities. On 32- and 64-Mbit densities this pin is a no-connect (NC).

23

3. A exists on 256-Mbit densities. On 32-, 64- and 128-Mbit densities this pin is a no-connect (NC).

24

4. V = 5 V ± 10% for the 28F640J5/28F320J5.

CC

Preliminary

5

28F128J3A, 28F640J3A, 28F320J3A

2.0

Principles of Operation

The Intel StrataFlash memory devices include an on-chip WSM to manage block erase, program,

and lock-bit configuration functions. It allows for 100% TTL-level control inputs, fixed power

supplies during block erasure, program, lock-bit configuration, and minimal processor overhead

with RAM-like interface timings.

After initial device power-up or return from reset/power-down mode (see Section 3.0, “Bus

Operations” on page 7), the device defaults to read array mode. Manipulation of external memory

control pins allows array read, standby, and output disable operations.

Read array, status register, query, and identifier codes can be accessed through the CUI (Command

User Interface) independent of the V_PENvoltage. V_PENHon V_PENenables successful block

erasure, programming, and lock-bit configuration. All functions associated with altering memory

contents—block erase, program, lock-bit configuration—are accessed via the CUI and verified

through the status register.

Commands are written using standard micro-processor write timings. The CUI contents serve as

input to the WSM, which controls the block erase, program, and lock-bit configuration. The

internal algorithms are regulated by the WSM, including pulse repetition, internal verification, and

margining of data. Addresses and data are internally latched during program cycles.

Interface software that initiates and polls progress of block erase, program, and lock-bit

configuration can be stored in any block. This code is copied to and executed from system RAM

during flash memory updates. After successful completion, reads are again possible via the Read

Array command. Block erase suspend allows system software to suspend a block erase to read or

program data from/to any other block. Program suspend allows system software to suspend a

program to read data from any other flash memory array location.

2.1

Data Protection

Depending on the application, the system designer may choose to make the V_PENswitchable

(available only when memory block erases, programs, or lock-bit configurations are required) or

hardwired to V_PENH. The device accommodates either design practice and encourages

optimization of the processor-memory interface.

When V_PEN≤ V_PENLK, memory contents cannot be altered. The CUI’s two-step block erase, byte/

word program, and lock-bit configuration command sequences provide protection from unwanted

operations even when V_PENHis applied to V_PEN. All program functions are disabled when V_CCis

below the write lockout voltage V_LKOor when RP# is V_IL. The device’s block locking capability

provides additional protection from inadvertent code or data alteration by gating erase and program

operations.

6

Preliminary

28F128J3A, 28F640J3A, 28F320J3A

3.0

Bus Operations

The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash

memory conform to standard microprocessor bus cycles.

Figure 4. Memory Map

A [23-0]:128 Mbit

A [22-0]: 64 Mbit

A [21-0]: 32 Mbit

A [23-1]: 128 Mbit

A [22-1]: 64 Mbit

A [21-1]: 32 Mbit

FFFFFF

FE0000

7FFFFF

7F0000

127

128-Kbyte Block

64-Kword Block

7FFFFF

7E0000

3FFFFF

3F0000

63

31

63

31

128-Kbyte Block

64-Kword Block

3FFFFF

3E0000

1FFFFF

1F0000

03FFFF

01FFFF

1

0

1

0

128-Kbyte Block

64-Kword Block

020000

01FFFF

010000

00FFFF

000000

Byte-Wide (x8) Mode

Word Wide (x16) Mode

Table 2. Chip Enable Truth Table

CE

0

DEVICE

2

1

V

IL

Enabled

Disabled

Enabled

Disabled

IL

V

IH

IL

IH

V

IL

V

IL

IH

V

IH

IL

V

IL

IH

V

IH

IL

V

IH

NOTE: For single-chip applications, CE and CE can be strapped to GND.

2

1

Preliminary

7

28F128J3A, 28F640J3A, 28F320J3A

3.1

Read

Information can be read from any block, query, identifier codes, or status register independent of

the V_PENvoltage.

Upon initial device power-up or after exit from reset/power-down mode, the device automatically

resets to read array mode. Otherwise, write the appropriate read mode command (Read Array, Read

Query, Read Identifier Codes, or Read Status Register) to the CUI. Six control pins dictate the data

flow in and out of the component: CE₀, CE₁, CE₂, OE#, WE#, and RP#. The device must be

enabled (see Table 2, “Chip Enable Truth Table” on page 7), and OE# must be driven active to

obtain data at the outputs. CE₀, CE₁, and CE₂are the device selection controls and, when enabled

(see Table 2), select the memory device. OE# is the data output (DQ₀–DQ₁₅) control and, when

active, drives the selected memory data onto the I/O bus. WE# must be at V_IH.

When reading information in read array mode, the device defaults to asynchronous page mode.

This mode provides high data transfer rate for memory subsystems. In this state, data is internally

read and stored in a high-speed page buffer. A_2:0addresses data in the page buffer. The page size is

four words or eight bytes. Asynchronous word/byte mode is supported with no additional

commands required.

3.2

3.3

Output Disable

With OE# at a logic-high level (V_IH), the device outputs are disabled. Output pins DQ₀–DQ₁₅are

placed in a high-impedance state.

Standby

CE₀, CE₁, and CE₂can disable the device (see Table 2) and place it in standby mode which

substantially reduces device power consumption. DQ₀–DQ₁₅outputs are placed in a high-

impedance state independent of OE#. If deselected during block erase, program, or lock-bit

configuration, the WSM continues functioning, and consuming active power until the operation

completes.

3.4

Reset/Power-Down

RP# at V_ILinitiates the reset/power-down mode.

In read modes, RP#-low deselects the memory, places output drivers in a high-impedance state, and

turns off numerous internal circuits. RP# must be held low for a minimum of t_PLPH. Time t_PHQVis

required after return from reset mode until initial memory access outputs are valid. After this wake-

up interval, normal operation is restored. The CUI is reset to read array mode and status register is

set to 80H.

During block erase, program, or lock-bit configuration modes, RP#-low will abort the operation. In

default mode, STS transitions low and remains low for a maximum time of t_PLPH+ t_PHRHuntil the

reset operation is complete. Memory contents being altered are no longer valid; the data may be

partially corrupted after a program or partially altered after an erase or lock-bit configuration. Time

t_PHWLis required after RP# goes to logic-high (V_IH) before another command can be written.

8

Preliminary

28F128J3A, 28F640J3A, 28F320J3A

As with any automated device, it is important to assert RP# during system reset. When the system

comes out of reset, it expects to read from the flash memory. Automated flash memories provide

status information when accessed during block erase, program, or lock-bit configuration modes. If

a CPU reset occurs with no flash memory reset, proper initialization may not occur because the

flash memory may be providing status information instead of array data. Intel^®Flash memories

allow proper initialization following a system reset through the use of the RP# input. In this

application, RP# is controlled by the same RESET# signal that resets the system CPU.

3.5

3.6

Read Query

The read query operation outputs block status information, CFI (Common Flash Interface) ID

string, system interface information, device geometry information, and Intel-specific extended

query information.

Read Identifier Codes

The read identifier codes operation outputs the manufacturer code, device code and the block lock

configuration codes for each block (see Figure 5 on page 10). Using the manufacturer and device

codes, the system CPU can automatically match the device with its proper algorithms. The block

lock configuration codes identify locked and unlocked blocks.

3.7

Write

Writing commands to the CUI enables reading of device data, query, identifier codes, inspection

and clearing of the status register, and, when V_PEN= V_PENH, block erasure, program, and lock-bit

configuration.

The Block Erase command requires appropriate command data and an address within the block to

be erased. The Byte/Word Program command requires the command and address of the location to

be written. Set Block Lock-Bit commands require the command and block within the device to be

locked. The Clear Block Lock-Bits command requires the command and address within the device.

The CUI does not occupy an addressable memory location. It is written when the device is enabled

and WE# is active. The address and data needed to execute a command are latched on the rising

edge of WE# or the first edge of CE₀, CE₁, or CE₂that disables the device (see Table 2). Standard

microprocessor write timings are used.

4.0

Command Definitions

When the V_PENvoltage ≤ V_PENLK, only read operations from the status register, query, identifier

codes, or blocks are enabled. Placing V_PENHon V_PENadditionally enables block erase, program,

and lock-bit configuration operations.

Device operations are selected by writing specific commands into the CUI. Table 4 defines these

commands.

Preliminary

9

28F128J3A, 28F640J3A, 28F320J3A

Figure 5. Device Identifier Code Memory Map

A[23-1]: 128 Mbit

A[22-1]: 64 Mbit

A[21-1]: 32 Mbit

Word

Address

7FFFFF

Block 127

Reserved for Future

Implementation

7F0003

7F0002

Block 127 Lock Configuration

Reserved for Future

Implementation

7F0000

7EFFFF

(Blocks 64 through 126)

3FFFFF

Block 63

Reserved for Future

Implementation

3F0003

3F0002

Block 63 Lock Configuration

Reserved for Future

Implementation

3F0000

3EFFFF

(Blocks 32 through 62)

Block 31

Reserved for Future

Implementation

1F0003

1F0002

Block 31 Lock Configuration

Reserved for Future

Implementation

1F0000

1EFFFF

(Blocks 2 through 30)

01FFFF

Block 1

Reserved for Future

Implementation

010003

010002

Block 1 Lock Configuration

Reserved for Future

Implementation

010000

00FFFF

Block 0

Reserved for Future

Implementation

000004

000003

000002

000001

000000

Block 0 Lock Configuration

Device Code

Manufacturer Code

0606-06a

NOTE:

A is not used in either x8 or x16 modes when obtaining these identifier codes. Data is always given on the low byte in

0

x16 mode (upper byte contains 00h).

10

Preliminary

28F128J3A, 28F640J3A, 28F320J3A

Table 3. Bus Operations

STS

(default

mode)

(1)

0,1,2

Mode

Notes

RP#

CE

OE#⁽²⁾

WE#⁽²⁾Address

V

DQ⁽³⁾

PEN

Read Array

4,5,6

V

Enabled

Disabled

V

X

D

High Z⁽⁷⁾

IH

IL

IH

OUT

Output Disable

Standby

V

High Z

X

IH

X

Reset/Power-Down

Mode

V

X

High Z

Note 8

Note 9

High Z⁽⁷⁾

IL

See

Figure 5

Read Identifier Codes

V

Enabled

V

IH

IL

IH

See

Table 7

Read Query

V

Enabled

V

X

IH

IL

IH

Read Status (WSM off)

X

D

OUT

IL

IH

DQ = D

7

OUT

Read Status (WSM on)

Write

V

Enabled

V

X

DQ

15–8

= High Z

IH

IL

IH

DQ

6–0

6,10,11

V

D

IN

X

IH

IL

PENH

NOTES:

1. See Table 2 for valid CE configurations.

2. OE# and WE# should never be enabled simultaneously.

3. DQ refers to DQ DQ if BYTE# is low and DQ DQ if BYTE# is high.

0–

7

0–

15

4. Refer to DC Characteristics. When V

≤ V

, memory contents can be read, but not altered.

PEN

PENLK

5. X can be V or V for control and address pins, and V

or V

for V

. See DC Characteristics for

PEN

IL

IH

PENLK

PENH

V

and V

voltages.

PENLK

PENH

6. In default mode, STS is V when the WSM is executing internal block erase, program, or lock-bit

OL

configuration algorithms. It is V

when the WSM is not busy, in block erase suspend mode (with

OH

programming inactive), program suspend mode, or reset/power-down mode.

7. High Z will be V with an external pull-up resistor.

OH

8. See Section 3.6 for read identifier code data.

9. See Section 4.2 for read query data.

10.Command writes involving block erase, program, or lock-bit configuration are reliably executed when V

=

PEN

V

and V is within specification.

PENH

CC

11.Refer to Table 4 for valid D during a write operation.

IN

Preliminary

11

28F128J3A, 28F640J3A, 28F320J3A

Table 4. Intel^®StrataFlash™ Memory Command Set Definitions⁽¹⁾

Scalable or

Bus

Basic

Command

Cycles Notes

Req’d.

First Bus Cycle

Second Bus Cycle

Command

Set⁽²⁾

Oper⁽³⁾

Addr⁽⁴⁾

Data^(5,6)

Oper⁽³⁾

Addr⁽⁴⁾

Data^(5,6)

Read Array

SCS/BCS

SCS

1

Write

X

FFH

90H

98H

70H

50H

Read Identifier Codes

Read Query

≥ 2

2

7

8

Read

IA

QA

X

ID

QD

Read Status Register

Clear Status Register

SCS/BCS

SRD

1

9, 10,

11

Write to Buffer

SCS/BCS

> 2

2

Write

BA

X

E8H

Write

BA

N

40H

or

10H

Word/Byte Program

Block Erase

12,13

Write

PA

BA

PD

SCS/BCS

2

1

11,12

12,14

Write

BA

X

20H

B0H

D0H

Block Erase, Program

Suspend

Block Erase, Program

Resume

SCS/BCS

1

12

Write

X

D0H

Configuration

SCS

2

Write

X

B8H

60H

C0H

Write

X

BA

X

CC

01H

D0H

PD

Set Block Lock-Bit

Clear Block Lock-Bits

Protection Program

15

PA

NOTES:

1. Commands other than those shown above are reserved by Intel for future device implementations and

should not be used.

2. The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command

Set. The Scalable Command Set (SCS) is also referred to as the Intel Extended Command Set.

3. Bus operations are defined in Table 3.

4. X = Any valid address within the device.

BA = Address within the block.

IA = Identifier Code Address: see Figure 5 and Table 15.

QA = Query database Address.

PA = Address of memory location to be programmed.

RCD = Data to be written to the read configuration register. This data is presented to the device on A

other address inputs are ignored.

; all

16-1

5. ID = Data read from Identifier Codes.

QD = Data read from Query database.

SRD = Data read from status register. See Table 16 for a description of the status register bits.

PD = Data to be programmed at location PA. Data is latched on the rising edge of WE#.

CC = Configuration Code.

6. The upper byte of the data bus (DQ DQ ) during command writes is a “Don’t Care” in x16 operation.

8–

15

7. Following the Read Identifier Codes command, read operations access manufacturer, device and block lock

codes. See Section 4.3 for read identifier code data.

8. If the WSM is running, only DQ is valid; DQ DQ and DQ DQ float, which places them in a high-

7

15–

8

6–

0

impedance state.

9. After the Write to Buffer command is issued check the XSR to make sure a buffer is available for writing.

12

Preliminary

28F128J3A, 28F640J3A, 28F320J3A

10.The number of bytes/words to be written to the Write Buffer = N + 1, where N = byte/word count argument.

Count ranges on this device for byte mode are N = 00H to N = 1FH and for word mode are N = 0000H to N =

000FH. The third and consecutive bus cycles, as determined by N, are for writing data into the Write Buffer.

The Confirm command (D0H) is expected after exactly N + 1 write cycles; any other command at that point in

the sequence aborts the write to buffer operation. Please see Figure 7, “Write to Buffer Flowchart” on

page 30 for additional information.

11.The write to buffer or erase operation does not begin until a Confirm command (D0h) is issued.

12.Attempts to issue a block erase or program to a locked block.

13.Either 40H or 10H are recognized by the WSM as the byte/word program setup.

14.Program suspends can be issued after either the Write-to-Buffer or Word-/Byte-Program operation is

initiated.

15.The clear block lock-bits operation simultaneously clears all block lock-bits.

4.1

Read Array Command

Upon initial device power-up and after exit from reset/power-down mode, the device defaults to

read array mode. The read configuration register defaults to asynchronous read page mode. The

Read Array command also causes the device to enter read array mode. The device remains enabled

for reads until another command is written. Once the internal WSM has started a block erase,

program, or lock-bit configuration, the device will not recognize the Read Array command until

the WSM completes its operation unless the WSM is suspended via an Erase or Program Suspend

command. The Read Array command functions independently of the V_PENvoltage.

4.2

Read Query Mode Command

This section defines the data structure or “database” returned by the Common Flash Interface (CFI)

Query command. System software should parse this structure to gain critical information such as

block size, density, x8/x16, and electrical specifications. Once this information has been obtained,

the software will know which command sets to use to enable flash writes, block erases, and

otherwise control the flash component. The Query is part of an overall specification for multiple

command set and control interface descriptions called Common Flash Interface, or CFI.

4.2.1

Query Structure Output

The Query “database” allows system software to gain information for controlling the flash

component. This section describes the device’s CFI-compliant interface that allows the host system

to access Query data.

Query data are always presented on the lowest-order data outputs (DQ_0–7) only. The numerical

offset value is the address relative to the maximum bus width supported by the device. On this

family of devices, the Query table device starting address is a 10h, which is a word address for x16

devices.

For a word-wide (x16) device, the first two bytes of the Query structure, “Q” and “R” in ASCII,

appear on the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00H

data on upper bytes. Thus, the device outputs ASCII “Q” in the low byte (DQ_0–7) and 00h in the

high byte (DQ_8–15).

At Query addresses containing two or more bytes of information, the least significant data byte is

presented at the lower address, and the most significant data byte is presented at the higher address.

Preliminary

13

28F128J3A, 28F640J3A, 28F320J3A

In all of the following tables, addresses and data are represented in hexadecimal notation, so the

“h” suffix has been dropped. In addition, since the upper byte of word-wide devices is always

“00h,” the leading “00” has been dropped from the table notation and only the lower byte value is

shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode.

Table 5. Summary of Query Structure Output as a Function of Device and Mode

Device

Type/

Mode

Query start location in

maximum device bus

width addresses

Query data with maximum

device bus width addressing

Query data with byte

addressing

Hex

Offset

Hex

Code

ASCII

Value

Hex

Offset

Hex

Code

ASCII

Value

x16 device

x16 mode

10h

10:

11:

12:

0051

0052

0059

“Q”

“R”

“Y”

20:

21:

22:

20:

21:

22:

51

00

52

51

52

“Q”

“Null”

“R”

x16 device

x8 mode

“Q”

N/A⁽¹⁾

“Q”

“R”

NOTE:

1. The system must drive the lowest order addresses to access all the device’s array data when the device is

configured in x8 mode. Therefore, word addressing, where these lower addresses are not toggled by the

system, is "Not Applicable" for x8-configured devices.

Table 6. Example of Query Structure Output of a x16- and x8-Capable Device

Word Addressing

Hex Code

Byte Addressing

Hex Code

Offset

–A

Value

Offset

Value

A

D15–D

A –A

D –D

7 0

15

0

7

0

0010h

0011h

0012h

0013h

0014h

0015h

0016h

0017h

0018h

...

0051

0052

0059

“Q”

“R”

20h

21h

22h

23h

24h

25h

26h

27h

28h

...

51

“Q”

“Y”

52

“R”

P_ID

PrVendor

ID #

52

“R”

LO

P_ID

59

“Y”

HI

P

PrVendor

TblAdr

AltVendor

ID #

59

“Y”

LO

P

P_ID

PrVendor

ID #

...

HI

LO

A_ID

LO

A_ID

...

P_ID

...

HI

...

4.2.2

Query Structure Overview

The Query command causes the flash component to display the Common Flash Interface (CFI)

Query structure or “database.” The structure sub-sections and address locations are summarized

below. See AP-646 Common Flash Interface (CFI) and Command Sets (order number 292204) for

a full description of CFI.

The following sections describe the Query structure sub-sections in detail.

14

Preliminary

28F128J3A, 28F640J3A, 28F320J3A

Table 7. Query Structure⁽¹⁾

Offset

Sub-Section Name

Description

00h

01h

Manufacturer Code

Device Code

(BA+2)h⁽²⁾

04-0Fh

10h

Block Status Register

Reserved

Block-Specific Information

Reserved for Vendor-Specific Information

Command Set ID and Vendor Data Offset

Flash Device Layout

CFI Query Identification String

System Interface Information

Device Geometry Definition

1Bh

27h

Primary Intel-Specific Extended

Query Table

Vendor-Defined Additional Information Specific to the

Primary Vendor Algorithm

P⁽³⁾

NOTES:

1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a

function of device bus width and mode.

2. BA = Block Address beginning location (i.e., 02000h is block 2’s beginning location when the block size is

128 Kbyte).

3. Offset 15 defines “P” which points to the Primary Intel-Specific Extended Query Table.

4.2.3

Block Status Register

The block status register indicates whether an erase operation completed successfully or whether a

given block is locked or can be accessed for flash program/erase operations.

Table 8. Block Status Register

Offset

(BA+2)h⁽¹⁾

Length

Description

Block Lock Status Register

Address

Value

1

BA+2:

--00 or --01

BSR.0 Block Lock Status

0 = Unlocked

1 = Locked

BA+2:

(bit 0): 0 or 1

BSR 1–7: Reserved for Future Use

(bit 1–7): 0

NOTE:

1. BA = The beginning location of a Block Address (i.e., 008000h is block 1’s (64-KB block) beginning location

in word mode).

4.2.4

CFI Query Identification String

The CFI Query Identification String provides verification that the component supports the

Common Flash Interface specification. It also indicates the specification version and supported

vendor-specified command set(s).

Table 9. CFI Identification

Hex

Code

Offset Length

Description

Add.

Value

10

11:

12:

13:

14:

15:

16:

--51

--52

--59

--01

--00

--31

--00

“Q”

“R”

“Y”

10h

13h

15h

3

2

Query-unique ASCII string “QRY”

Primary vendor command set and control interface ID code.

16-bit ID code for vendor-specified algorithms

Extended Query Table primary algorithm address

Preliminary

15

28F128J3A, 28F640J3A, 28F320J3A

Table 9. CFI Identification

Hex

Code

Offset Length

Description

Add.

Value

17h

19h

2

Alternate vendor command set and control interface ID code.

0000h means no second vendor-specified algorithm exists

Secondary algorithm Extended Query Table address.

0000h means none exists

17:

18:

19:

1A:

--00

4.2.5

System Interface Information

The following device information can optimize system interface software.

Table 10. System Interface Information

Hex

Code

Offset Length

Description

Add.

Value

V

logic supply minimum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 BCD volts

CC

1Bh

1Ch

1Dh

1Eh

1

1B:

--27

--36

--00

2.7 V

logic supply maximum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 BCD volts

CC

1C:

1D:

1E:

3.6 V

0.0 V

[programming] supply minimum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 HEX volts

PP

[programming] supply maximum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 HEX volts

PP

1Fh

20h

21h

22h

1

“n” such that typical single word program time-out = 2ⁿµs

“n” such that typical max. buffer write time-out = 2ⁿµs

“n” such that typical block erase time-out = 2ⁿms

“n” such that typical full chip erase time-out = 2ⁿms

“n” such that maximum word program time-out = 2ⁿtimes

typical

1F:

20:

21:

22:

--07

--0A

--00

128 µs

1 s

NA

23h

1

23:

--04

2 ms

24h

25h

26h

1

“n” such that maximum buffer write time-out = 2ⁿtimes typical

“n” such that maximum block erase time-out = 2ⁿtimes typical

“n” such that maximum chip erase time-out = 2ⁿtimes typical

24:

25:

26:

--04

--00

2 ms

16 s

NA

16

Preliminary

28F128J3A, 28F640J3A, 28F320J3A

4.2.6

Device Geometry Definition

This field provides critical details of the flash device geometry.

Table 11. Device Geometry Definition

Code See Table

Below

Offset Length

Description

27h

28h

1

“n” such that device size = 2ⁿin number of bytes

27:

x8/

x16

2

Flash device interface: x8 async x16 async x8/x16 async

28:

--02

28:00,29:00 28:01,29:00 28:02,29:00

“n” such that maximum number of bytes in write buffer = 2ⁿ

29:

2A:

2B:

--00

--05

--00

2Ah

2

1

32

Number of erase block regions within device:

1. x = 0 means no erase blocking; the device erases in “bulk”

2. x specifies the number of device or partition regions with one or

more contiguous same-size erase blocks

2Ch

2C:

--01

1

3. Symmetrically blocked partitions have one blocking region

4. Partition size = (total blocks) x (individual block size)

Erase Block Region 1 Information

2D:

2E:

2F:

30:

bits 0–15 = y, y+1 = number of identical-size erase blocks

bits 16–31 = z, region erase block(s) size are z x 256 bytes

2Dh

4

Device Geometry Definition

Address

32 Mbit

64 Mbit

128 Mbit

27:

28:

29:

2A:

2B:

2C:

2D:

2E:

2F:

30:

--16

--02

--00

--05

--00

--01

--1F

--00

--02

--17

--02

--00

--05

--00

--01

--3F

--00

--02

--18

--02

--00

--05

--00

--01

--7F

--00

--02

Preliminary

17

28F128J3A, 28F640J3A, 28F320J3A

4.2.7

Primary-Vendor Specific Extended Query Table

Certain flash features and commands are optional. The Primary Vendor-Specific Extended Query

table specifies this and other similar information.

Table 12. Primary Vendor-Specific Extended Query

Offset⁽¹⁾

P = 31h

Description

(Optional Flash Features and Commands)

Hex

Code

Length

Add.

Value

(P+0)h

(P+1)h

(P+2)h

(P+3)h

(P+4)h

3

Primary extended query table

31:

32:

33:

34:

35:

36:

37:

38:

39:

--50

--52

--49

--31

--0A

--00

“P”

“R”

“I”

Unique ASCII string “PRI”

1

Major version number, ASCII

“1”

Minor version number, ASCII

Optional feature and command support (1=yes, 0=no)

bits 9–31 are reserved; undefined bits are “0.” If bit 31 is

“1” then another 31 bit field of optional features follows at

the end of the bit-30 field.

bit 0 Chip erase supported

bit 0 = 0

No

Yes

Yes⁽¹⁾

No

(P+5)h

(P+6)h

(P+7)h

(P+8)h

bit 1 Suspend erase supported

bit 1 = 1

bit 2 = 1

bit 3 = 1⁽¹⁾

bit 4 = 0

bit 5 = 0

bit 6 = 1

bit 7 = 1

bit 8 = 0

4

bit 2 Suspend program supported

bit 3 Legacy lock/unlock supported

bit 4 Queued erase supported

bit 5 Instant Individual block locking supported

bit 6 Protection bits supported

No

Yes

No

bit 7 Page-mode read supported

bit 8 Synchronous read supported

Supported functions after suspend: read Array, Status,

Query

Other supported operations are:

bits 1–7 reserved; undefined bits are “0”

3A:

--01

(P+9)h

1

2

bit 0 Program supported after erase suspend

Block status register mask

bit 0 = 1

3B:

3C:

bit 0 = 1

bit 1 = 0

Yes

--01

--00

(P+A)h

(P+B)h

bits 2–15 are Reserved; undefined bits are “0”

bit 0 Block Lock-Bit Status register active

bit 1 Block Lock-Down Bit Status active

Yes

No

V

logic supply highest performance program/erase

CC

voltage

bits 0–3 BCD value in 100 mV

bits 4–7 BCD value in volts

optimum program/erase supply voltage

bits 0–3 BCD value in 100 mV

bits 4–7 HEX value in volts

(P+C)h

(P+D)h

1

3D:

--33

--00

3.3 V

0.0 V

V

PP

3E:

NOTE:

1. Future devices may not support the described “Legacy Lock/Unlock” function. Thus bit 3 would have a value

of “0.”

18

Preliminary

28F128J3A, 28F640J3A, 28F320J3A

Table 13. Protection Register Information

Offset⁽¹⁾

P = 31h

Description

(Optional Flash Features and Commands)

Hex

Code

Length

Add.

Value

Number of Protection register fields in JEDEC ID space.

“00h,” indicates that 256 protection bytes are available

(P+E)h

1

4

3F:

--01

01

Protection Field 1: Protection Description

This field describes user-available One Time Programmable

(OTP) protection register bytes. Some are pre-programmed

with device-unique serial numbers. Others are user-

programmable. Bits 0-15 point to the protection register lock

byte, the section’s first byte. The following bytes are factory

pre-programmed and user-programmable.

(P+F)h

(P+10)h

(P+11)h

(P+12)h

40:

--00

00h

bits 0-7 = Lock/bytes JEDEC-plane physical low address

bits 8-15 = Lock/bytes JEDEC-plane physical high address

bits 16-23 = “n” such that 2ⁿ= factory pre-programmed bytes

bits 24-31 = “n” such that 2ⁿ= user-programmable bytes

NOTE:

1. The variable P is a pointer which is defined at CFI offset 15h.

Table 14. Burst Read Information

Offset⁽¹⁾

P = 31h

Description

(Optional Flash Features and Commands)

Hex

Code

Length

Add.

Value

Page Mode Read capability

bits 0–7 = “n” such that 2ⁿHEX value represents the number

of read-page bytes. See offset 28h for device word width to

determine page-mode data output width. 00h indicates no

read page buffer.

(P+13)h

1

44:

--03

--00

8 byte

0

Number of synchronous mode read configuration fields that

follow. 00h indicates no burst capability.

(P+14)h

(P+15)h

45:

46:

Reserved for future use

NOTE:

1. The variable P is a pointer which is defined at CFI offset 15h.

4.3

Read Identifier Codes Command

The identifier code operation is initiated by writing the Read Identifier Codes command. Following

the command write, read cycles from addresses shown in Figure 5 on page 10 retrieve the

manufacturer, device and block lock configuration codes (see Table 15 for identifier code values).

Page-mode reads are not supported in this read mode. To terminate the operation, write another

valid command. Like the Read Array command, the Read Identifier Codes command functions

independently of the V_PENvoltage. This command is valid only when the WSM is off or the device

is suspended. Following the Read Identifier Codes command, the following information can be

read:

Preliminary

19

28F128J3A, 28F640J3A, 28F320J3A

Table 15. Identifier Codes

Code

Address⁽¹⁾

Data

Manufacture Code

00000

00001

X0002⁽²⁾

(00) 89

(00) 16

(00) 17

(00) 18

Device Code

32-Mbit

64-Mbit

128-Mbit

Block Lock Configuration

• Block Is Unlocked

DQ = 0

0

• Block Is Locked

DQ = 1

0

• Reserved for Future Use

DQ

1–7

NOTES:

1. A is not used in either x8 or x16 modes when obtaining the identifier codes. The lowest order address line is

0

A . Data is always presented on the low byte in x16 mode (upper byte contains 00h).

1

2. X selects the specific block’s lock configuration code. See Figure 5 for the device identifier code memory

map.

4.4

Read Status Register Command

The status register may be read to determine when a block erase, program, or lock-bit configuration

is complete and whether the operation completed successfully. It may be read at any time by

writing the Read Status Register command. After writing this command, all subsequent read

operations output data from the status register until another valid command is written. Page-mode

reads are not supported in this read mode. The status register contents are latched on the falling

edge of OE# or the first edge of CE₀, CE₁, or CE₂that enables the device (see Table 2, “Chip

Enable Truth Table” on page 7). OE# must toggle to V_IHor the device must be disabled (see Table

2) before further reads to update the status register latch. The Read Status Register command

functions independently of the V_PENvoltage.

During a program, block erase, set lock-bit, or clear lock-bit command sequence, only SR.7 is valid

until the Write State Machine completes or suspends the operation. Device I/O pins DQ₀–DQ₆and

DQ₈–DQ₁₅are placed in a high-impedance state. When the operation completes or suspends

(check status register bit 7), all contents of the status register are valid when read.

20

Preliminary

28F128J3A, 28F640J3A, 28F320J3A

Table 16. Status Register Definitions

WSMS

bit 7

ESS

bit 6

ECLBS

bit 5

PSLBS

bit 4

VPENS

bit 3

PSS

bit2

DPS

bit 1

R

bit 0

High Z

When

Busy?

Status Register Bits

Notes

SR.7 = WRITE STATE MACHINE STATUS

Check STS or SR.7 to determine block erase,

program, or lock-bit configuration completion. SR.6–

SR.0 are not driven while SR.7 = “0.”

No

1 = Ready

0 = Busy

Yes

SR.6 = ERASE SUSPEND STATUS

1 = Block Erase Suspended

0 = Block Erase in Progress/Completed

If both SR.5 and SR.4 are “1”s after a block erase or

lock-bit configuration attempt, an improper

command sequence was entered.

SR.5 = ERASE AND CLEAR LOCK-BITSSTATUS

1 = Error in Block Erasure or Clear Lock-Bits

0 = Successful Block Erase or Clear Lock-Bits

Yes

SR.4 = PROGRAM AND SET LOCK-BIT STATUS

1 = Error in Setting Lock-Bit

0 = Successful Set Block Lock Bit

SR.3 does not provide a continuous programming

voltage level indication. The WSM interrogates and

indicates the programming voltage level only after

Block Erase, Program, Set Block Lock-Bit, or Clear

Block Lock-Bits command sequences.

SR.3 = PROGRAMMING VOLTAGE STATUS

1 = Low Programming Voltage Detected, Operation

Aborted

0 = Programming Voltage OK

Yes

SR.2 = PROGRAM SUSPEND STATUS

1 = Program suspended

0 = Program in progress/completed

SR.1 does not provide a continuous indication of

block lock-bit values. The WSM interrogates the

block lock-bits only after Block Erase, Program, or

Lock-Bit configuration command sequences. It

informs the system, depending on the attempted

operation, if the block lock-bit is set. Read the block

lock configuration codes using the Read Identifier

Codes command to determine block lock-bit status.

SR.1 = DEVICE PROTECT STATUS

1 = Block Lock-Bit Detected, Operation Abort

0 = Unlock

SR.0 is reserved for future use and should be

masked when polling the status register.

Yes

SR.0 = RESERVED FOR FUTURE ENHANCEMENTS

Table 17. eXtended Status Register Definitions

WBS

bit 7

Reserved

bits 6—0

High Z

When

Busy?

Status Register Bits

Notes

After a Buffer-Write command, XSR.7 = 1 indicates

that a Write Buffer is available.

XSR.7 = WRITE BUFFER STATUS

1 = Write buffer available

No

0 = Write buffer not available

SR.6–SR.0 are reserved for future use and should

Yes

be masked when polling the status register.

XSR.6–XSR.0 = RESERVED FOR FUTURE

ENHANCEMENTS

Preliminary

21

28F128J3A, 28F640J3A, 28F320J3A

4.5

Clear Status Register Command

Status register bits SR.5, SR.4, SR.3, and SR.1 are set to “1”s by the WSM and can only be reset by

the Clear Status Register command. These bits indicate various failure conditions (see Table 16).

By allowing system software to reset these bits, several operations (such as cumulatively erasing or

locking multiple blocks or writing several bytes in sequence) may be performed. The status register

may be polled to determine if an error occurred during the sequence.

To clear the status register, the Clear Status Register command (50H) is written. It functions

independently of the applied V_PENvoltage. The Clear Status Register command is only valid when

the WSM is off or the device is suspended.

4.6

Block Erase Command

Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is

first written, followed by an block erase confirm. This command sequence requires an appropriate

address within the block to be erased (erase changes all block data to FFH). Block preconditioning,

erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle

block erase sequence is written, the device automatically outputs status register data when read (see

Figure 10, “Block Erase Flowchart” on page 33). The CPU can detect block erase completion by

analyzing the output of the STS pin or status register bit SR.7. Toggle OE#, CE₀, CE₁, or CE₂to

update the status register.

When the block erase is complete, status register bit SR.5 should be checked. If a block erase error

is detected, the status register should be cleared before system software attempts corrective actions.

The CUI remains in read status register mode until a new command is issued.

This two-step command sequence of set-up followed by execution ensures that block contents are

not accidentally erased. An invalid Block Erase command sequence will result in both status

register bits SR.4 and SR.5 being set to “1.” Also, reliable block erasure can only occur when V_CC

is valid and V_PEN= V_PENH. If block erase is attempted while V_PEN≤ V_PENLK, SR.3 and SR.5 will

be set to “1.” Successful block erase requires that the corresponding block lock-bit be cleared. If

block erase is attempted when the corresponding block lock-bit is set, SR.1 and SR.5 will be set to

“1.”

4.7

Block Erase Suspend Command

The Block Erase Suspend command allows block-erase interruption to read or program data in

another block of memory. Once the block erase process starts, writing the Block Erase Suspend

command requests that the WSM suspend the block erase sequence at a predetermined point in the

algorithm. The device outputs status register data when read after the Block Erase Suspend

command is written. Polling status register bit SR.7 then SR.6 can determine when the block erase

operation has been suspended (both will be set to “1”). In default mode, STS will also transition to

V

_OH. Specification t_WHRHdefines the block erase suspend latency.

At this point, a Read Array command can be written to read data from blocks other than that which

is suspended. A program command sequence can also be issued during erase suspend to program

data in other blocks. During a program operation with block erase suspended, status register bit

SR.7 will return to “0” and STS output (in default mode) will transition to V_OL. However, SR.6

will remain “1” to indicate block erase suspend status. Using the Program Suspend command, a

program operation can also be suspended. Resuming a suspended programming operation by

22

Preliminary

28F128J3A, 28F640J3A, 28F320J3A

issuing the Program Resume command allows continuing of the suspended programming

operation. To resume the suspended erase, the user must wait for the programming operation to

complete before issuing the Block Erase Resume command.

The only other valid commands while block erase is suspended are Read Query, Read Status

Register, Clear Status Register, Configure, and Block Erase Resume. After a Block Erase Resume

command is written to the flash memory, the WSM will continue the block erase process. Status

register bits SR.6 and SR.7 will automatically clear and STS (in default mode) will return to V_OL

After the Erase Resume command is written, the device automatically outputs status register data

when read (see Figure 11, “Block Erase Suspend/Resume Flowchart” on page 34). V_PENmust

.

remain at V_PENH(the same V_PENlevel used for block erase) while block erase is suspended. Block

erase cannot resume until program operations initiated during block erase suspend have completed.

4.8

Write to Buffer Command

To program the flash device, a Write to Buffer command sequence is initiated. A variable number

of bytes, up to the buffer size, can be loaded into the buffer and written to the flash device. First, the

Write to Buffer Setup command is issued along with the Block Address (see Figure 7, “Write to

Buffer Flowchart” on page 30). At this point, the eXtended Status Register (XSR, see Table 17)

information is loaded and XSR.7 reverts to “buffer available” status. If XSR.7 = 0, the write buffer

is not available. To retry, continue monitoring XSR.7 by issuing the Write to Buffer setup

command with the Block Address until XSR.7 = 1. When XSR.7 transitions to a “1,” the buffer is

ready for loading.

Now a word/byte count is given to the part with the Block Address. On the next write, a device

start address is given along with the write buffer data. Subsequent writes provide additional device

addresses and data, depending on the count. All subsequent addresses must lie within the start

address plus the count.

Internally, this device programs many flash cells in parallel. Because of this parallel programming,

maximum programming performance and lower power are obtained by aligning the start address at

the beginning of a write buffer boundary (i.e., A₄–A₀of the start address = 0).

After the final buffer data is given, a Write Confirm command is issued. This initiates the WSM

(Write State Machine) to begin copying the buffer data to the flash array. If a command other than

Write Confirm is written to the device, an “Invalid Command/Sequence” error will be generated

and Status Register bits SR.5 and SR.4 will be set to a “1.” For additional buffer writes, issue

another Write to Buffer Setup command and check XSR.7.

If an error occurs while writing, the device will stop writing, and status register bit SR.4 will be set

to a “1” to indicate a program failure. The internal WSM verify only detects errors for “1”s that do

not successfully program to “0”s. If a program error is detected, the status register should be

cleared. Any time SR.4 and/or SR.5 is set (e.g., a media failure occurs during a program or an

erase), the device will not accept any more Write to Buffer commands. Additionally, if the user

attempts to program past an erase block boundary with a Write to Buffer command, the device will

abort the write to buffer operation. This will generate an “Invalid Command/Sequence” error and

status register bits SR.5 and SR.4 will be set to a “1.”

Reliable buffered writes can only occur when V_PEN= V_PENH. If a buffered write is attempted

while V_PEN≤ V_PENLK, status register bits SR.4 and SR.3 will be set to “1.” Buffered write attempts

with invalid V_CCand V_PENvoltages produce spurious results and should not be attempted. Finally,

successful programming requires that the corresponding block lock-bit be reset. If a buffered write

is attempted when the corresponding block lock-bit is set, SR.1 and SR.4 will be set to “1.”

Preliminary

23

28F128J3A, 28F640J3A, 28F320J3A

4.9

Byte/Word Program Commands

Byte/Word program is executed by a two-cycle command sequence. Byte/Word program setup

(standard 40H or alternate 10H) is written followed by a second write that specifies the address and

data (latched on the rising edge of WE#). The WSM then takes over, controlling the program and

program verify algorithms internally. After the program sequence is written, the device

automatically outputs status register data when read (see Figure 8, “Byte/Word Program

Flowchart” on page 31). The CPU can detect the completion of the program event by analyzing the

STS pin or status register bit SR.7.

When program is complete, status register bit SR.4 should be checked. If a program error is

detected, the status register should be cleared. The internal WSM verify only detects errors for “1”s

that do not successfully program to “0”s. The CUI remains in read status register mode until it

receives another command.

Reliable byte/word programs can only occur when V_CCand V_PENare valid. If a byte/word

program is attempted while V_PEN≤ V_PENLK, status register bits SR.4 and SR.3 will be set to “1.”

Successful byte/word programs require that the corresponding block lock-bit be cleared. If a byte/

word program is attempted when the corresponding block lock-bit is set, SR.1 and SR.4 will be set

to “1.”

4.10

Program Suspend Command

The Program Suspend command allows program interruption to read data in other flash memory

locations. Once the programming process starts (either by initiating a write to buffer or byte/word

program operation), writing the Program Suspend command requests that the WSM suspend the

program sequence at a predetermined point in the algorithm. The device continues to output status

register data when read after the Program Suspend command is written. Polling status register bits

SR.7 can determine when the programming operation has been suspended. When SR.7 = 1, SR.2

should also be set to “1”, indicating that the device is in the program suspend mode. STS in level

RY/BY# mode will also transition to V_OH. Specification t_WHRH1defines the program suspend

latency.

At this point, a Read Array command can be written to read data from locations other than that

which is suspended. The only other valid commands while programming is suspended are Read

Query, Read Status Register, Clear Status Register, Configure, and Program Resume. After a

Program Resume command is written, the WSM will continue the programming process. Status

register bits SR.2 and SR.7 will automatically clear and STS in RY/BY# mode will return to V_OL

After the Program Resume command is written, the device automatically outputs status register

data when read. V_PENmust remain at V_PENHand V_CCmust remain at valid V_CClevels (the same

.

V

_PENand V_CClevels used for programming) while in program suspend mode. Refer to Figure 9,

“Program Suspend/Resume Flowchart” on page 32.

4.11

Set Read Configuration Command

This command is not support on this product. This device will default to the asynchronous page

mode. If this command is given to the device it will not effect the operation of the device.

24

Preliminary

28F128J3A, 28F640J3A, 28F320J3A

4.11.1

Read Configuration

The device will support both asynchronous page mode and standard word/byte reads. No

configuration is required.

Status register and identifier only support standard word/byte single read operations.

Table 18. Read Configuration Register Definition

RM

R

15

R

14

R

13

R

12

R

11

R

10

R

9

16 (A

)

16

R

8

R

1

7

6

5

4

3

2

Notes

RCR.16 = READ MODE (RM)

0 = Standard Word/Byte Reads Enabled (Default)

1 = Page-Mode Reads Enabled

Read mode configuration effects reads from the flash array.

Status register, query, and identifier reads support standard

word/byte read cycles.

RCR.15–1 = RESERVED FOR FUTURE ENHANCEMENTS (R) These bits are reserved for future use. Set these bits to “0.”

4.12

Configuration Command

The Status (STS) pin can be configured to different states using the Configuration command. Once

the STS pin has been configured, it remains in that configuration until another configuration

command is issued or RP# is asserted low. Initially, the STS pin defaults to RY/BY# operation

where RY/BY# low indicates that the state machine is busy. RY/BY# high indicates that the state

machine is ready for a new operation or suspended. Table 19, “Configuration Coding Definitions”

on page 26 displays the possible STS configurations.

To reconfigure the Status (STS) pin to other modes, the Configuration command is given followed

by the desired configuration code. The three alternate configurations are all pulse mode for use as a

system interrupt as described below. For these configurations, bit 0 controls Erase Complete

interrupt pulse, and bit 1 controls Program Complete interrupt pulse. Supplying the 00h

configuration code with the Configuration command resets the STS pin to the default RY/BY#

level mode. The possible configurations and their usage are described in Table 19, “Configuration

Coding Definitions” on page 26. The Configuration command may only be given when the device

is not busy or suspended. Check SR.7 for device status. An invalid configuration code will result in

both status register bits SR.4 and SR.5 being set to “1.” When configured in one of the pulse

modes, the STS pin pulses low with a typical pulse width of 250 ns.

Preliminary

25

28F128J3A, 28F640J3A, 28F320J3A

Table 19. Configuration Coding Definitions

Pulse on

Program

Pulse on

Erase

Reserved

Complete⁽¹⁾

Compete⁽¹⁾

bits 7—2

bit 1

bit 0

DQ DQ = Reserved

7–

2

DQ DQ are reserved for future use.

7–

2

DQ DQ = STS Pin Configuration Codes

1–

0

default (DQ DQ = 00) RY/BY#, level mode

1–

0

00 = default, level mode RY/BY#

(device ready) indication

— used to control HOLD to a memory controller to prevent

accessing a flash memory subsystem while any flash device's

WSM is busy.

01 = pulse on Erase complete

10 = pulse on Program complete

11 = pulse on Erase or Program Complete

configuration 01 ER INT, pulse mode

— used to generate a system interrupt pulse when any flash

device in an array has completed a Block Erase. Helpful for

reformatting blocks after file system free space reclamation or

“cleanup”

Configuration Codes 01b, 10b, and 11b are all pulse mode

such that the STS pin pulses low then high when the

operation indicated by the given configuration is completed.

configuration 10 PR INT, pulse mode

Configuration Command Sequences for STS pin

— used to generate a system interrupt pulse when any flash

device in an array has complete a Program operation. Provides

highest performance for servicing continuous buffer write

operations.

configuration (masking bits DQ DQ to 00h) are as follows:

7–

2

Default RY/BY# level mode: B8h, 00h

ER INT (Erase Interrupt): B8h, 01h

Pulse-on-Erase Complete

PR INT (Program Interrupt): B8h, 02h

Pulse-on-Program Complete

configuration 11 ER/PR INT, pulse mode

— used to generate system interrupts to trigger servicing of flash

arrays when either erase or program operations are completed

when a common interrupt service routine is desired.

ER/PR INT (Erase or Program Interrupt): B8h, 03h

Pulse-on-Erase or Program Complete

NOTE: 1. When the device is configured in one of the pulse modes, the STS pin pulses low with a typical pulse

width of 250 ns.

4.13

Set Block Lock-Bit Commands

A flexible block locking and unlocking scheme is enabled via block lock-bits. The block lock-bits

gate program and erase operations. Individual block lock-bits can be set using the Set Block Lock-

Bit command. This command is invalid while the WSM is running or the device is suspended.

Set block lock-bit commands are executed by a two-cycle sequence. The set block setup along with

appropriate block address is followed by either the set block lock-bit confirm (and an address

within the block to be locked). The WSM then controls the set lock-bit algorithm. After the

sequence is written, the device automatically outputs status register data when read (see Figure 12

on page 35). The CPU can detect the completion of the set lock-bit event by analyzing the STS pin

output or status register bit SR.7.

When the set lock-bit operation is complete, status register bit SR.4 should be checked. If an error

is detected, the status register should be cleared. The CUI will remain in read status register mode

until a new command is issued.

This two-step sequence of set-up followed by execution ensures that lock-bits are not accidentally

set. An invalid Set Block Lock-Bit command will result in status register bits SR.4 and SR.5 being

set to “1.” Also, reliable operations occur only when V_CCand V_PENare valid. With V_PEN

≤

V

_PENLK, lock-bit contents are protected against alteration.

26

Preliminary

28F128J3A, 28F640J3A, 28F320J3A

4.14

Clear Block Lock-Bits Command

All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. Block lock-

bits can be cleared using only the Clear Block Lock-Bits command. This command is invalid while

the WSM is running or the device is suspended.

Clear block lock-bits command is executed by a two-cycle sequence. A clear block lock-bits setup

is first written. The device automatically outputs status register data when read (see Figure 13 on

page 36). The CPU can detect completion of the clear block lock-bits event by analyzing the STS

pin output or status register bit SR.7.

When the operation is complete, status register bit SR.5 should be checked. If a clear block lock-bit

error is detected, the status register should be cleared. The CUI will remain in read status register

mode until another command is issued.

This two-step sequence of set-up followed by execution ensures that block lock-bits are not

accidentally cleared. An invalid Clear Block Lock-Bits command sequence will result in status

register bits SR.4 and SR.5 being set to “1.” Also, a reliable clear block lock-bits operation can

only occur when V_CCand V_PENare valid. If a clear block lock-bits operation is attempted while

V_PEN≤ V_PENLK, SR.3 and SR.5 will be set to “1.”

If a clear block lock-bits operation is aborted due to V_PENor V_CCtransitioning out of valid range,

block lock-bit values are left in an undetermined state. A repeat of clear block lock-bits is required

to initialize block lock-bit contents to known values.

4.15

Protection Register Program Command

The 3 Volt Intel StrataFlash memory includes a 128-bit protection register that can be used to

increase the security of a system design. For example, the number contained in the protection

register can be used to “mate” the flash component with other system components such as the CPU

or ASIC, preventing device substitution.

The 128-bits of the protection register are divided into two 64-bit segments. One of the segments is

programmed at the Intel factory with a unique 64-bit number, which is unchangeable. The other

segment is left blank for customer designers to program as desired. Once the customer segment is

programmed, it can be locked to prevent reprogramming.

4.15.1

4.15.2

Reading the Protection Register

The protection register is read in the identification read mode. The device is switched to this mode

by writing the Read Identifier command (90H). Once in this mode, read cycles from addresses

shown in Table 20 or Table 21 retrieve the specified information. To return to read array mode,

write the Read Array command (FFH).

Programming the Protection Register

The protection register bits are programmed using the two-cycle Protection Program command.

The 64-bit number is programmed 16 bits at a time for word-wide parts and eight bits at a time for

byte-wide parts. First write the Protection Program Setup command, C0H. The next write to the

Preliminary

27

28F128J3A, 28F640J3A, 28F320J3A

device will latch in address and data and program the specified location. The allowable addresses

are shown in Table 20 or Table 21. See Figure 14, “Protection Register Programming Flowchart”

on page 37

Any attempt to address Protection Program commands outside the defined protection register

address space will result in a status register error (program error bit SR.4 will be set to 1).

Attempting to program a locked protection register segment will result in a status register error

(program error bit SR.4 and lock error bit SR.1 will be set to 1).

4.15.3

Locking the Protection Register

The user-programmable segment of the protection register is lockable by programming Bit 1 of the

PR-LOCK location to 0. Bit 0 of this location is programmed to 0 at the Intel factory to protect the

unique device number. Bit 1 is set using the Protection Program command to program “FFFD” to

the PR-LOCK location. After these bits have been programmed, no further changes can be made to

the values stored in the protection register. Protection Program commands to a locked section will

result in a status register error (program error bit SR.4 and Lock Error bit SR.1 will be set to 1).

Protection register lockout state is not reversible.

Figure 6. Protection Register Memory Map

A[23 - 1]: 128 Mbit

A[22 - 1]: 64 Mbit

Word

Address A[21 - 1]: 32 Mbit

88H

4 Words

User Programmed

85H

84H

4 Words

Factory Programmed

81H

1 Word Lock

80H

0667_06

NOTE: A is not used in x16 mode when accessing the protection register map (See Table 20 for x16

0

addressing). For x8 mode A is used (See Table 21 for x8 addressing).

0

28

Preliminary

28F128J3A, 28F640J3A, 28F320J3A

Table 20. Word-Wide Protection Register Addressing

Word

Use

Both

A8

1

A7

0

A6

0

A5

0

A4

0

A3

0

A2

0

A1

0

LOCK

0

1

2

3

4

5

6

7

Factory

User

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

User

1

0

1

0

User

1

0

1

User

1

0

1

0

NOTE: 1. All address lines not specified in the above table must be 0 when accessing the Protection Register,

i.e., A –A = 0.

23

9

Table 21. Byte-Wide Protection Register Addressing

Byte

Use

A8

A7

A6

A5

A4

A3

A2

A1

LOCK

Both

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

LOCK

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

Factory

User

NOTE: 1. All address lines not specified in the above table must be 0 when accessing the Protection Register,

i.e., A –A = 0.

23

9

Preliminary

29

28F128J3A, 28F640J3A, 28F320J3A

Figure 7. Write to Buffer Flowchart

Start

Bus

Operation

Command

Comments

Data = E8H

Set Time-Out

Write

Read

Write to Buffer

Block Address

Issue Write to Buffer

Command E8H, Block

Address

No

XSR. 7 = Valid

Addr = Block Address

Check XSR. 7

Read Extended

Status Register

Standby

1 = Write Buffer Available

0 = Write Buffer Not Available

Data = N = Word/Byte Count

N = 0 Corresponds to Count = 1

Addr = Block Address

Write

(Note 1, 2)

0

Write to

Buffer Time-Out?

XSR.7 =

1

Write

(Note 3, 4)

Data = Write Buffer Data

Addr = Device Start Address

Write Word or Byte

Count, Block Address

Write

(Note 5, 6)

Data = Write Buffer Data

Addr = Device Address

Program Buffer

to Flash

Confirm

Data = D0H

Addr = Block Address

Write Buffer Data,

Start Address

Write

Status Register Data with the

Device Enabled, OE# Low

Updates SR

X = 0

Read

(Note 7)

Yes

Addr = Block Address

Check SR.7

1 = WSM Ready

0 = WSM Busy

Check

X = N?

Standby

No

Yes

1. Byte or word count values on DQ - DQ₇are loaded into the

0

count register. Count ranges on this device for byte mode are

= 00H to 1FH and for word mode are N = 0000H to 000FH.

2. The device now outputs the status register when read (XSR is

no longer available).

N

Abort Write to

Buffer Command?

Yes Write to Another

Block Address

3. Write Buffer contents will be programmed at the device start

address or destination flash address.

4. Align the start address on a Write Buffer boundary for

Yes

No

Write to Buffer

Aborted

Write Next Buffer Data,

Device Address

maximum programming performance (i.e., A - A₀of the start

4

address = 0).

5. The device aborts the Write to Buffer command if the current

address is outside of the original block address.

6. The status register indicates an "improper command

sequence" if the Write to Buffer command is aborted. Follow this

with a Clear Status Register command.

X = X + 1

Program Buffer to Flash

Confirm D0H

7. Toggling OE# (low to high to low) updates the status register.

This can be done in place of issuing the Read Status Register

command.

Another Write to

Buffer?

Full status check can be done after all erase and write sequences

complete. Write FFH after the last operation to reset the device to

read array mode.

Issue Read

Status Command

No

Read Status Register

1

0

SR.7 =

1

Full Status

Check if Desired

Programming

Complete

0606_07A

30

Preliminary

28F128J3A, 28F640J3A, 28F320J3A

Figure 8. Byte/Word Program Flowchart

Start

Bus

Operation

Command

Comments

Setup Byte/

Data = 40H

Write 40H,

Address

Write

Word Program Addr = Location to Be Programmed

Byte/Word

Program

Data = Data to Be Programmed

Addr = Location to Be Programmed

Write Data and

Address

Read

(Note 1)

Status Register Data

Check SR.7

1 = WSM Ready

0 = WSM Busy

Read Status

Register

Standby

1. Toggling OE# (low to high to low) updates the status register. This

can be done in place of issuing the Read Status Register command.

Repeat for subsequent programming operations.

0

SR.7 =

SR full status check can be done after each program operation, or

after a sequence of programming operations.

1

Full Status

Write FFH after the last program operation to place device in read

array mode.

Check if Desired

Byte/Word

Program Complete

FULL STATUS CHECK PROCEDURE

Bus

Operation

Command

Comments

Check SR.3

1 = Programming to Voltage Error

Detect

Read Status

Register Data

(See Above)

Standby

1

Check SR.1

SR.3 =

SR.1 =

SR.4 =

Voltage Range Error

1 = Device Protect Detect

RP# = V_IH, Block Lock-Bit Is Set

Only required for systems

implemeting lock-bit configuration.

Standby

0

1

Check SR.4

1 = Programming Error

Device Protect Error

Programming Error

Toggling OE# (low to high to low) updates the status register. This can

be done in place of issuing the Read Status Register command.

Repeat for subsequent programming operations.

SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register

command in cases where multiple locations are programmed before

full status is checked.

Byte/Word

Program

Successful

If an error is detected, clear the status register before attempting retry

or other error recovery.

Preliminary

31

28F128J3A, 28F640J3A, 28F320J3A

Figure 9. Program Suspend/Resume Flowchart

Bus

Operation

Start

Command

Comments

Data = B0H

Program

Suspend

Write

Read

Addr = X

Write B0H

Status Register Data

Addr = X

Check SR.7

Standby

1 - WSM Ready

0 = WSM Busy

Read Status Register

Check SR.6

1 = Programming Suspended

0 = Programming Completed

0

SR.7 =

Data = FFH

Addr = X

Write

Read

Write

Read Array

1

Read array locations other

than that being programmed.

0

SR.2 =

Programming Completed

Program

Resume

Data = D0H

Addr = X

1

Write FFH

Read Data Array

No

Done Reading

Yes

Write D0H

Write FFH

Programming Resumed

Read Array Data

0606_08

32

Preliminary

28F128J3A, 28F640J3A, 28F320J3A

Figure 10. Block Erase Flowchart

Bus

Operation

Command

Comments

Data = 20H

Start

Write

Erase Block

Addr = Block Address

Erase

Confirm

Data = D0H

Addr = X

Write (Note 1)

Read

Issue Single Block Erase

Command 20H, Block

Address

Status register data

With the device enabled,

OE# low updates SR

Addr = X

Check SR.7

Standby

1 = WSM Ready

0 = WSM Busy

Write Confirm D0H

Block Address

1. The Erase Confirm byte must follow Erase Setup.

This device does not support erase queuing. Please see

Application note AP-646 For software erase queuing

compatibility.

Read

Status Register

Full status check can be done after all erase and write

sequences complete. Write FFH after the last operation to

reset the device to read array mode.

No

Suspend

Erase Loop

0

Yes

SR.7 =

Suspend Erase

1

Full Status

Check if Desired

Erase Flash

Block(s) Complete

0606_09

Preliminary

33

28F128J3A, 28F640J3A, 28F320J3A

Figure 11. Block Erase Suspend/Resume Flowchart

Bus

Operation

Start

Command

Comments

Data = B0H

Write

Read

Erase Suspend

Addr = X

Write B0H

Status Register Data

Addr = X

Check SR.7

Standby

1 - WSM Ready

0 = WSM Busy

Read Status Register

Check SR.6

Standby

Write

1 = Block Erase Suspended

0 = Block Erase Completed

0

SR.7 =

Data = D0H

Addr = X

Erase Resume

1

0

SR.6 =

Block Erase Completed

1

Read

Program

Read or Program?

Read Array

Data

Program

Loop

No

Done?

Yes

Write D0H

Write FFH

Block Erase Resumed

Read Array Data

0606_10

34

Preliminary

28F128J3A, 28F640J3A, 28F320J3A

Figure 12. Set Block Lock-Bit Flowchart

Start

Bus

Operation

Command

Comments

Set Block Lock-Bit Data = 60H

Write 60H,

Block Address

Write

Setup

Addr =Block Address

Set Block Lock-Bit Data = 01H

Write

Read

Confirm

Addr = Block Address

Write 01H,

Block Address

Status Register Data

Check SR.7

1 = WSM Ready

0 = WSM Busy

Read Status Register

Standby

Repeat for subsequent lock-bit operations.

0

SR.7 =

Full status check can be done after each lock-bit set operation or after

a sequence of lock-bit set operations.

1

Write FFH after the last lock-bit set operation to place device in read

array mode.

Full Status

Check if Desired

Set Lock-Bit Complete

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

Bus

Operation

Command

Comments

Check SR.3

1 = Programming Voltage Error

Detect

1

Standby

SR.3 =

Voltage Range Error

Check SR.4, 5

Standby

Both 1 = Command Sequence

Error

0

SR.4,5 =

0

1

Command Sequence

Error

Check SR.4

1 = Set Lock-Bit Error

SR.5, SR.4 and SR.3 are only cleared by the Clear Status Register

command, in cases where multiple lock-bits are set before full status is

checked.

SR.4 =

0

Set Lock-Bit Error

If an error is detected, clear the status register before attempting retry

or other error recovery.

Set Lock-Bit

Successful

0606_11b

Preliminary

35

28F128J3A, 28F640J3A, 28F320J3A

Figure 13. Clear Lock-Bit Flowchart

Start

Write 60H

Bus

Operation

Command

Comments

Data = 60H

Clear Block

Lock-Bits Setup

Write

Addr = X

Clear Block or

Lock-Bits Confirm

Data = D0H

Addr = X

Write

Read

Write D0H

Status Register Data

Check SR.7

1 = WSM Ready

0 = WSM Busy

Read Status Register

Standby

Write FFH after the clear lock-bits operation to place device in read

array mode.

0

SR.7 =

1

Full Status

Check if Desired

Clear Block Lock-Bits

Complete

FULL STATUS CHECK PROCEDURE

Bus

Operation

Command

Comments

Read Status Register

Data (See Above)

Check SR.3

Standby

1 = Programming Voltage Error

Detect

1

SR.3 =

0

Voltage Range Error

Check SR.4, 5

Both 1 = Command Sequence

Error

Standby

1

Check SR.5

1 = Clear Block Lock-Bits Error

Command Sequence

Error

SR.4,5 =

0

SR.5, SR.4, and SR.3 are only cleared by the Clear Status Register

command.

Clear Block Lock-Bits

Error

SR.5 =

0

If an error is detected, clear the status register before attempting retry

or other error recovery.

Clear Block Lock-Bits

Successful

0606_12b

36

Preliminary

28F128J3A, 28F640J3A, 28F320J3A

Figure 14. Protection Register Programming Flowchart

Start

Bus Operation

Command

Comments

Protection Program

Setup

Write

Data = C0H

Write C0H

(Protection Reg.

Program Setup)

Data = Data to Program

Addr = Location to Program

Protection Program

Status Register Data Toggle

CE# or OE# to Update Status

Register Data

Write Protect. Register

Address/Data

Read

Check SR.7

Standby

1 = WSM Ready

0 = WSM Busy

Read Status Register

Protection Program operations can only be addressed within the protection

register address space. Addresses outside the defined space will return an

error.

No

SR.7 = 1?

Yes

Repeat for subsequent programming operations.

SR Full Status Check can be done after each program or after a sequence of

program operations.

Full Status

Check if Desired

Write FFH after the last program operation to reset device to read array mode.

Program Complete

FULL STATUS CHECK PROCEDURE

Bus Operation

Standby

Command

Comments

SR.1 SR.3 SR.4

Read Status Register

Data (See Above)

0

1

V_PENLow

1, 1

0

1

Prot. Reg.

Prog. Error

Standby

SR.3, SR.4 =

SR.1, SR.4 =

V_PENRange Error

1

0

1

Register

Locked:

Aborted

0,1

1,1

Standby

Protection Register

Programming Error

SR.3 MUST be cleared, if set during a program attempt, before further

attempts are allowed by the Write State Machine.

Attempted Program to

Locked Register -

Aborted

SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command,

in cases of multiple protection register program operations before full status is

checked.

SR.1, SR.4 =

If an error is detected, clear the status register before attempting retry or other

error recovery.

Program Successful

Preliminary

37

28F128J3A, 28F640J3A, 28F320J3A

5.0

Design Considerations

5.1

Three-Line Output Control

The device will often be used in large memory arrays. Intel provides five control inputs (CE₀, CE₁,

CE₂, OE#, and RP#) to accommodate multiple memory connections. This control provides for:

a. Lowest possible memory power dissipation.

b. Complete assurance that data bus contention will not occur.

To use these control inputs efficiently, an address decoder should enable the device (see Table 2)

while OE# should be connected to all memory devices and the system’s READ# control line. This

assures that only selected memory devices have active outputs while de-selected memory devices

are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent

unintended writes during system power transitions. POWERGOOD should also toggle during

system reset.

5.2

STS and Block Erase, Program, and Lock-Bit Configuration

Polling

STS is an open drain output that should be connected to V_CCQby a pull-up resistor to provide a

hardware method of detecting block erase, program, and lock-bit configuration completion. It is

recommended that a 2.5k resister be used between STS# and V_CCQ. In default mode, it transitions

low after block erase, program, or lock-bit configuration commands and returns to High Z when

the WSM has finished executing the internal algorithm. For alternate configurations of the STS

pin, see the Configuration command.

STS can be connected to an interrupt input of the system CPU or controller. It is active at all times.

STS, in default mode, is also High Z when the device is in block erase suspend (with programming

inactive), program suspend, or in reset/power-down mode.

5.3

Power Supply Decoupling

Flash memory power switching characteristics require careful device decoupling. System designers

are interested in three supply current issues; standby current levels, active current levels and

transient peaks produced by falling and rising edges of CE₀, CE₁, CE₂, and OE#. Transient current

magnitudes depend on the device outputs’ capacitive and inductive loading. Two-line control and

proper decoupling capacitor selection will suppress transient voltage peaks. Since Intel StrataFlash

memory devices draw their power from three V_CCpins (these devices do not include a V_PPpin), it

is recommended that systems without separate power and ground planes attach a 0.1 µF ceramic

capacitor between each of the device’s three V_CCpins (this includes V_CCQ) and ground. These

high-frequency, low-inductance capacitors should be placed as close as possible to package leads

on each Intel StrataFlash memory device. Each device should have a 0.1 µF ceramic capacitor

connected between its V_CCand GND. These high-frequency, low inductance capacitors should be

placed as close as possible to package leads. Additionally, for every eight devices, a 4.7 µF

electrolytic capacitor should be placed between V_CCand GND at the array’s power supply

connection. The bulk capacitor will overcome voltage slumps caused by PC board trace

inductance.

38

Preliminary

28F128J3A, 28F640J3A, 28F320J3A

5.4

Input Signal Transitions - Reducing Overshoots and

Undershoots When Using Buffers or Transceivers

As faster, high-drive devices such as transceivers or buffers drive input signals to flash memory

devices, overshoots and undershoots can sometimes cause input signals to exceed flash memory

specifications. (See “Absolute Maximum Ratings” on page 40.) Many buffer/transceiver vendors

now carry bus-interface devices with internal output-damping resistors or reduced-drive outputs.

Internal output-damping resistors diminish the nominal output drive currents, while still leaving

sufficient drive capability for most applications. These internal output-damping resistors help

reduce unnecessary overshoots and undershoots. Transceivers or buffers with balanced- or light-

drive outputs also reduce overshoots and undershoots by diminishing output-drive currents. When

considering a buffer/transceiver interface design to flash, devices with internal output-damping

resistors or reduced-drive outputs should be used to minimize overshoots and undershoots. For

additional information, please refer to the AP-647 5 Volt Intel StrataFlash™ Memory Design

Guide.

5.5

V , V

, RP# Transitions

PEN

CC

Block erase, program, and lock-bit configuration are not guaranteed if V_PENor V_CCfalls outside of

the specified operating ranges, or RP# ≠ V_IH. If RP# transitions to V_ILduring block erase,

program, or lock-bit configuration, STS (in default mode) will remain low for a maximum time of

t

_PLPH+ t_PHRHuntil the reset operation is complete. Then, the operation will abort and the device

will enter reset/power-down mode. The aborted operation may leave data partially corrupted after

programming, or partially altered after an erase or lock-bit configuration. Therefore, block erase

and lock-bit configuration commands must be repeated after normal operation is restored. Device

power-off or RP# = V_ILclears the status register.

The CUI latches commands issued by system software and is not altered by V_PEN, CE₀, CE₁, or

CE₂transitions, or WSM actions. Its state is read array mode upon power-up, after exit from reset/

power-down mode, or after V_CCtransitions below V_LKO. V_CCmust be kept at or above V_PEN

during V_CCtransitions.

After block erase, program, or lock-bit configuration, even after V_PENtransitions down to V_PENLK

the CUI must be placed in read array mode via the Read Array command if subsequent access to

the memory array is desired. V_PENmust be kept at or below V_CCduring V_PENtransitions.

,

5.6

Power-Up/Down Protection

The device is designed to offer protection against accidental block erasure, programming, or lock-

bit configuration during power transitions. Internal circuitry resets the CUI to read array mode at

power-up.

A system designer must guard against spurious writes for V_CCvoltages above V_LKOwhen V_PENis

active. Since WE# must be low and the device enabled (see Table 2) for a command write, driving

WE# to V_IHor disabling the device will inhibit writes. The CUI’s two-step command sequence

architecture provides added protection against data alteration.

Keeping V_PENbelow V_PENLKprevents inadvertent data alteration. In-system block lock and

unlock capability protects the device against inadvertent programming. The device is disabled

while RP# = V_ILregardless of its control inputs.

Preliminary

39

28F128J3A, 28F640J3A, 28F320J3A

5.7

Power Dissipation

When designing portable systems, designers must consider battery power consumption not only

during device operation, but also for data retention during system idle time. Flash memory’s

nonvolatility increases usable battery life because data is retained when system power is removed.

6.0

Electrical Specifications

6.1

Absolute Maximum Ratings

Parameter

Temperature under Bias Expanded

Maximum Rating

–25 °C to +85 °C

Storage Temperature

Voltage On Any Pin

–65 °C to +125 °C

–2.0 V to +5.0 V⁽¹⁾

100 mA⁽²⁾

Output Short Circuit Current

NOTES:

1. All specified voltages are with respect to GND. Minimum DC voltage is –0.5 V on input/output pins and

–0.2 V on V and V pins. During transitions, this level may undershoot to –2.0 V for periods <20 ns.

CC

PEN

Maximum DC voltage on input/output pins, V , and V

is V +0.5 V which, during transitions, may

CC

PEN

CC

overshoot to V +2.0 V for periods <20 ns.

CC

2. Output shorted for no more than one second. No more than one output shorted at a time.

NOTICE: This datasheet contains preliminary information on new products in production. The specifications are

subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before

finalizing a design.

Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.

These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended

and extended exposure beyond the “Operating Conditions” may affect device reliability.

40

Preliminary

28F128J3A, 28F640J3A, 28F320J3A

6.2

Operating Conditions

Table 22. Temperature and V_CCOperating Conditions

Symbol

Parameter

Notes

Min

Max

Unit

Test Condition

T

Operating Temperature

–25

2.70

3.00

2.70

3.00

+85

3.60

°C

V

Ambient Temperature

A

V

Supply Voltage (2.7 V−3.6 V)

Supply Voltage (3.0 V−3.6 V)

CC1

V

CC2

Supply Voltage (2.7 V−3.6 V)

Supply Voltage (3.0 V−3.6 V)

V

CCQ1

CCQ2

CCQ1

CCQ2

V

6.3

Capacitance

T_A= +25 °C, f = 1 MHz

Symbol

Parameter⁽¹⁾

Typ

Max

Unit

Condition

C

Input Capacitance

Output Capacitance

6

8

pF

V

= 0.0 V

IN

12

= 0.0 V

OUT

NOTES:

1. Sampled, not 100% tested.

Preliminary

41

28F128J3A, 28F640J3A, 28F320J3A

6.4

DC Characteristics

Symbol

Parameter

Notes

Typ

Max

Unit

Test Conditions

V

= V Max; V

= V

Max

CC

CCQ

I

Input and V

Load Current

1

±1

µA

LI

PEN

= V

or GND

IN

CCQ

V

= V Max; V

CC CCQ

CC

Output Leakage Current

1

±10

µA

LO

= V

or GND

IN

CCQ

V

= V Max; V

CC CCQ

CC

Output Leakage Current

= V

or GND

IN

CCQ

CMOS Inputs, V = V Max,

CC

Device is enabled (see Table 2, “Chip

Enable Truth Table” on page 7),

50

120

µA

I

V

Standby Current

1,2,3,4

4

RP# = V

± 0.2 V

CCS

CC

CCQ

TTL Inputs, V = V Max,

CC

0.71

50

2

mA

Device is enabled (see Table 2), RP# = V

IH

Power-Down Current

120

µA

RP# = GND ± 0.2 V, I

(STS) = 0 mA

OUT

CCD

CMOS Inputs, V = V Max, V =

CCQ

CC

V

Max using standard 4 word page

CCQ

mode reads.

15

24

40

20

29

50

mA

Device is enabled (see Table 2)

f = 5 MHz, I

= 0 mA

OUT

I

V

Page Mode Read Current

1,3,4

CCR

CC

CMOS Inputs,V = V Max, V

Max using standard 4 word page mode

reads.

= V

CCQ

CC

CCQ

Device is enabled (see Table 2)

f = 33 MHz, I

= 0 mA

OUT

CMOS Inputs, V = V Max, V =

CCQ

CC

V

Max using standard word/byte single

CCQ

reads

Device is enabled (see Table 2)

f = 5 MHz, I = 0 mA

I

V

Byte Mode Read Current

Program or Set Lock-Bit

1,3,4

1,4,5

CCR

CC

OUT

35

40

35

40

60

70

80

mA

CMOS Inputs, V

= V

PEN

CC

I

CCW

Current

TTL Inputs, V

= V

PEN

CC

CMOS Inputs, V

TTL Inputs, V

= V

PEN

CC

V

Block Erase or Clear Block

CC

1,4,5

1,4,6

CCE

Lock-Bits Current

V Program Suspend or Block

CC

= V

PEN

CC

I

CCWS

CCES

10

mA

Device is disabled (see Table 2)

Erase Suspend Current

42

Preliminary

28F128J3A, 28F640J3A, 28F320J3A

DC Characteristics, Continued

Symbol

Parameter

Input Low Voltage

Notes

Min

Max

Unit

Test Conditions

V

5

–0.5

0.8

V

IL

Input High Voltage

2.0

V

+ 0.5

IH

CCQ

V

= V

= 2 mA

Min

CCQ

CCQ2/3

0.4

0.2

V

I

OL

V

Output Low Voltage

2,5

OL

V

= V

CCQ2/3

= 100 µA

CCQ

I

OL

0.85 ×

V

= V

= –2.5 mA

Min

CCQ

V

I

CCQ

OH

V

Output High Voltage

2,5

OH

V

= V

= –100 µA

Min

CCQ

V

– 0.2

CCQ

I

OH

V

Lockout during Program,

PEN

5,7,8

2.0

3.6

PENLK

Erase and Lock-Bit Operations

V

during Block Erase,

PEN

V

7,8

9

2.7

2.0

V

PENH

Program, or Lock-Bit Operations

V

Lockout Voltage

LKO

CC

NOTES:

1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages

and speeds). Contact Intel’s Application Support Hotline or your local sales office for information about typical

specifications.

2. Includes STS.

3. CMOS inputs are either V ± 0.2 V or GND ± 0.2 V. TTL inputs are either V or V .

CC

IL

IH

4. Current values are specified over the temperature range (0 °C to 70 °C) and may increase slightly at –25 °C.

5. Sampled, not 100% tested.

6. I

and I

are specified with the device de-selected. If the device is read or written while in erase

CCWS

CCES

suspend mode, the device’s current draw is I

or I

.

CCW

CCR

7. Block erases, programming, and lock-bit configurations are inhibited when V

≤ V

, and not

PEN

PENLK

guaranteed in the range between V

(max) and V

(min), and above V

(max).

PENLK

PENH

8. Typically, V

is connected to V (2.7 V–3.6 V).

PEN

CC

9. Block erases, programming, and lock-bit configurations are inhibited when V < V

, and not guaranteed

LKO

CC

in the range between V

(min) and V (min), and above V (max).

LKO

CC CC

Figure 15. Transient Input/Output Reference Waveform for V_CCQ= 3.0 V–3.6 V or

V

_CCQ= 2.7 V–3.6 V

V_CCQ

Input V_CCQ/2

0.0

Test Points

V_CCQ/2 Output

NOTE: AC test inputs are driven at V

for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and

CCQ

output timing ends, at V

/2 V (50% of V

). Input rise and fall times (10% to 90%) < 5 ns.

CCQ

Preliminary

43

28F128J3A, 28F640J3A, 28F320J3A

Figure 16. Transient Equivalent Testing Load Circuit

1.3V

1N914

R_L= 3.3 k

Ω

Device

Under Test

Out

C_L

NOTE: C Includes Jig Capacitance

L

Test Configuration

= V = 3.0 V−3.6 V

C (pF)

L

V

30

CCQ

CC

= V = 2.7 V−3.6 V

CCQ

CC

44

Preliminary

28F128J3A, 28F640J3A, 28F320J3A

6.5

AC Characteristics— Read-Only Operations^(1,2)

V

3.0 V–3.6 V ⁽³⁾

2.7 V–3.6 V ⁽³⁾

CC

Versions

(All units in ns unless otherwise noted)

V

CCQ

#

Sym

Parameter

Notes

Min

Max

Min

Max

32 Mbit

110

120

150

110

120

150

R1

t

Read/Write Cycle Time

64 Mbit

128 Mbit

32 Mbit

64 Mbit

128 Mbit

32 Mbit

64 Mbit

128 Mbit

AVAV

110

120

150

110

120

150

50

110

120

150

110

120

150

50

R2

Address to Output Delay

AVQV

2

R3

R4

R5

t

CEX to Output Delay

ELQV

GLQV

PHQV

2

OE# to Non-Array Output Delay

RP# High to Output Delay

2, 4

32 Mbit

64 Mbit

128 Mbit

150

180

210

150

180

210

R6

R7

R8

R9

t

CEX to Output in Low Z

5

0

ELQX

GLQX

EHQZ

GHQZ

OE# to Output in Low Z

CEX High to Output in High Z

OE# High to Output in High Z

55

15

55

15

Output Hold from Address, CEX, or OE# Change,

Whichever Occurs First

R10

t

5

0

OH

R11

R12

R13

R14

R15

R16

t

CEX Low to BYTE# High or Low

BYTE# to Output Delay

10

ELFL/ ELFH

t

1000

FLQV/ FHQV

BYTE# to Output in High Z

CEx High to CEx Low

5

FLQZ

EHEL

APA

Page Address Access Time

OE# to Array Output Delay

5, 6

4

25

30

GLQV

NOTES:

CE low is defined as the first edge of CE , CE , or CE that enables the device. CE high is defined at the first edge of CE ,

X

0

1

2

X

0

CE , or CE that disables the device (see Table 2).

1

2

1. See AC Input/Output Reference Waveforms for the maximum allowable input slew rate.

2. OE# may be delayed up to t

-t

after the first edge of CE , CE , or CE that enables the device (see

ELQV GLQV

0

1

2

Table 2) without impact on t

.

ELQV

3. See Figures 14–16, Transient Input/Output Reference Waveform for V

= 3.0 V –3.6 V or V

= 2.7 V –

CCQ

3.6 V, and Transient Equivalent Testing Load Circuit for testing characteristics.

4. When reading the flash array a faster t

query reads, or device identifier reads.

5. Sampled, not 100% tested.

(R16) applies. Non-array reads refer to status register reads,

GLQV

6. For devices configured to standard word/byte read mode, R15 (t

) will equal R2 (t

).

APA

AVQV

Preliminary

45

28F128J3A, 28F640J3A, 28F320J3A

Figure 17. AC Waveform for Both Page-Mode and Standard Word/Byte Read Operations

V_IH

ADDRESSES [A₂₃-A₃]

V_IL

R1

Valid

Address Address Address

V_IH

Valid

Address

Valid

ADDRESSES [A₂-A₀]

V_IL

R14

Disabled (V )

IH

CE_X[E]

Enabled (V )

IL

R8

R9

R2

R3

V_IH

OE# [G]

V_IL

V_IH

WE# [W]

V_IL

R4 or R16

R5

High Z

R15

Valid

R10

R6

V_OH

DATA [D/Q]

High Z

Valid

Output

DQ₀-DQ₁₅

Output Output Output

V_OL

V_IH

R7

V_CC

V_IL

V_IH

RP# [P]

R11

R12

V_IL

V_IH

R13

BYTE# [F]

V_IL

0606_16

NOTE: CE low is defined as the first edge of CE , CE , or CE that enables the device. CE high is defined at

X

0

1

2

X

the first edge of CE , CE , or CE that disables the device (see Table 2).

0

1

2

For standard word/byte read operations, R15 (t

) will equal R2 (t

).

APA

AVQV

When reading the flash array a faster t

(R16) applies. Non-array reads refer to status register

GLQV

reads, query reads, or device identifier reads.

46

Preliminary

28F128J3A, 28F640J3A, 28F320J3A

6.6

AC Characteristics— Write Operations^(1,2)

Valid for All

Speeds

Versions

Parameter

RP# High Recovery to WE# (CE ) Going Low

Unit

#

Symbol

(t

Notes

Min

Max

W1

W2

t

)

3

4

5

1

0

µs

ns

PHWL PHEL

X

(t

)

CE (WE#) Low to WE# (CE ) Going Low

ELWL WLEL

X

W3

Write Pulse Width

70

50

55

10

0

WP

W4

(t

)

Data Setup to WE# (CE ) Going High

X

DVWH DVEH

W5

(t

)

Address Setup to WE# (CE ) Going High

X

AVWH AVEH

W6

(t

)

CE (WE#) Hold from WE# (CE ) High

X X

WHEH EHWH

W7

(t

)

Data Hold from WE# (CE ) High

X

WHDX EHDX

W8

(t

)

Address Hold from WE# (CE ) High

0

WHAX EHAX

X

W9

Write Pulse Width High

6

3

30

0

WPH

W11

W12

W13

W15

(t

)

V

Setup to WE# (CE ) Going High

PEN X

VPWH VPEH

(t

)

Write Recovery before Read

WE# (CE ) High to STS Going Low

7

35

WHGL EHGL

(t

)

8

500

WHRL EHRL

X

V

Hold from Valid SRD, STS Going High

PEN

3,8,9

0

QVVL

NOTES:

CE low is defined as the first edge of CE , CE , or CE that enables the device. CE high is defined at the first edge of CE ,

X

0

1

2

X

0

CE , or CE that disables the device (see Table 2).

1

2

1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same

as during read-only operations. Refer to AC Characteristics–Read-Only Operations.

2. A write operation can be initiated and terminated with either CE or WE#.

X

3. Sampled, not 100% tested.

4. Write pulse width (t ) is defined from CE or WE# going low (whichever goes low first) to CE or WE# going

WP

X

high (whichever goes high first). Hence, t

= t

. If CE is driven low 10 ns

WP

WLWH

ELEH

WLEH

ELWH X

before WE# going low, WE# pulse width requirement decreases to t

- 10 ns.

WP

5. Refer to Table 4 for valid A and D for block erase, program, or lock-bit configuration.

IN

6. Write pulse width high (t

) is defined from CE or WE# going high (whichever goes high first) to CE or

WPH

X

WE# going low (whichever goes low first). Hence, t

= t

.

WPH

WHWL

EHEL

WHEL

EHWL

7. For array access, t

is required in addition to t

for any accesses after a write.

AVQV

WHGL

8. STS timings are based on STS configured in its RY/BY# default mode.

9. V should be held at V until determination of block erase, program, or lock-bit configuration success

PEN

PENH

(SR.1/3/4/5 = 0).

Preliminary

47

28F128J3A, 28F640J3A, 28F320J3A

6.7

Block Erase, Program, and Lock-Bit Configuration

Performance^(1,2,3)

#

Sym

Parameter

Notes

Typ

Max

Unit

Write Buffer Byte Program Time

(Time to Program 32 bytes/16 words)

W16

4,5,6,7

218

654

µs

t

Byte Program Time (Using Word/Byte Program

Command)

WHQV3

EHQV3

W16

4

210

0.8

1.0

630

2.4

5.0

µs

Block Program Time (Using Write to Buffer Command)

Block Erase Time

sec

t

WHQV4

EHQV4

W16

t

WHQV5

EHQV5

Set Lock-Bit Time

4

64

0.5

25

26

75

0.70

75

µs

sec

µs

t

WHQV6

EHQV6

Clear Block Lock-Bits Time

t

WHRH1

EHRH1

Program Suspend Latency Time to Read

Erase Suspend Latency Time to Read

t

WHRH

EHRH

35

µs

NOTES:

1. Typical values measured at T = +25 °C and nominal voltages. Assumes corresponding lock-bits are not set.

A

Subject to change based on device characterization.

2. These performance numbers are valid for all speed versions.

3. Sampled but not 100% tested.

4. Excludes system-level overhead.

5. These values are valid when the buffer is full, and the start address is aligned on a 32-byte boundary.

6. Effective per-byte program time (t

7. Effective per-word program time (t

, t

) is 6.8 µs/byte (typical)

) is 13.6 µs/word (typical)

WHQV1 EHQV1

, t

WHQV2 EHQV2

8. Max values are measured at worst case temperature and V corner after 100k cycles

CC

48

Preliminary

28F128J3A, 28F640J3A, 28F320J3A

Figure 18. AC Waveform for Write Operations

A

B

C

D

E

F

V_IH

V_IL

A_IN

ADDRESSES [A]

W5

W8

Disabled (V_IH)

CE_X, (WE#) [E(W)]

Enabled (V_IL)

W6

W12

W1

V_IH

OE# [G]

V_IL

W2

W9

W16

Disabled (V_IH)

WE#, (CE_X) [W(E)]

Enabled (V_IL)

W3

W4

High Z

W7

V_IH

Valid

SRD

D_IN

DATA [D/Q]

V_IL

W13

V_OH

STS [R]

V_OL

V_IH

RP# [P]

V_IL

W11

W15

V_PENH

V

V_PEN[V^P]^ENLK

V_IL

0606_17

NOTES:

CE low is defined as the first edge of CE , CE , or CE that enables the device. CE high is defined at the first edge of CE ,

X

0

1

2

X

0

CE , or CE that disables the device (see Table 2).

1

2

STS is shown in its default mode (RY/BY#).

a. V power-up and standby.

CC

b. Write block erase, write buffer, or program setup.

c. Write block erase or write buffer confirm, or valid address and data.

d. Automated erase delay.

e. Read status register or query data.

f. Write Read Array command.

Preliminary

49

28F128J3A, 28F640J3A, 28F320J3A

Figure 19. AC Waveform for Reset Operation

V

IH

STS (R)

V_IL

P2

V

IH

RP# (P)

V_IL

P1

0606_18

NOTE: STS is shown in its default mode (RY/BY#).

Reset Specifications⁽¹⁾

#

Sym

Parameter

Notes

Min

Max

Unit

RP# Pulse Low Time

P1

t

(If RP# is tied to V , this specification is not

applicable)

2

35

µs

ns

PLPH

CC

RP# High to Reset during Block Erase, Program, or

Lock-Bit Configuration

P2

3

100

PHRH

NOTES:

1. These specifications are valid for all product versions (packages and speeds).

2. If RP# is asserted while a block erase, program, or lock-bit configuration operation is not executing then the

minimum required RP# Pulse Low Time is 100 ns.

3. A reset time, t

valid.

, is required from the latter of STS (in RY/BY# mode) or RP# going high until outputs are

PHQV

50

Preliminary

28F128J3A, 28F640J3A, 28F320J3A

7.0

Ordering Information

R C 2 8 F 1 2 8 J 3 A - 1 5 0

Access Speed (ns)¹

128 Mbit = 150

64 Mbit = 120

Package

E = 56-Lead TSOP

RC = 64-Ball Easy BGA

32 Mbit = 110

Intel^®0.25 micron

ETOX™ VI Process

Technology

Product line designator

for all Intel^®Flash

products

Voltage (V_CC/V_PEN

)

3 = 3 V/3 V

Device Density

128 = x8/x16 (128 Mbit)

640 = x8/x16 (64 Mbit)

320 = x8/x16 (32 Mbit)

Product Family

J = Intel^®StrataFlash^TMmemory,

2 bits-per-cell

NOTE:

1. These speeds are for either the standard asynchronous read access times or for the first access of a page-

mode read sequence.

VALID COMBINATIONS

56-Lead TSOP

64-Ball Easy BGA

E28F128J3A-150

E28F640J3A-120

E28F320J3A-110

RC28F128J3A-150

RC28F640J3A-120

RC28F320J3A-110

Preliminary

51

28F128J3A, 28F640J3A, 28F320J3A

8.0

Additional Information

Order Number

Document/Tool

3 Volt Intel^®StrataFlash™ Memory 28F128J3A, 28F640J3A, 320J3A

Specification Update

298130

290668

292237

Note 3

Intel^®Persistent Storage Manager datasheet

AP-689 Using Intel^®Persistent Storage Manager

AP-707 3 Volt Intel^®StrataFlash™ Memory CPU Interface Design Guide

5 Volt Intel^®StrataFlash™ MemoryI28F320J5 and 28F640J5 datasheet

3 Volt FlashFile™ Memory; 28F160S3 and 28F320S3 datasheet

5 Volt FlashFile™ Memory; 28F160S5 and 28F320S5 datasheet

5 Volt FlashFile™ Memory; 28F008SA datasheet

290606

290608

290609

290429

290598

290597

297859

292222

292221

292218

292205

292204

292202

298161

Note 4

3 Volt FlashFile™ Memory; 28F004S3, 28F008S3, 28F016S3 datasheet

5 Volt FlashFile™ Memory; 28F004S5, 28F008S5, 28F016S5 datasheet

AP-677 Intel^®StrataFlash™ Memory Technology

AP-664 Designing Intel^®StrataFlash™ Memory into Intel^®Architecture

AP-663 Using the Intel^®StrataFlash™ Memory Write Buffer

AP-660 Migration Guide to 3 Volt Intel^®StrataFlash™ Memory

AP-647 5 Volt Intel^®StrataFlash™ Memory Design Guide

AP-646 Common Flash Interface (CFI) and Command Sets

AP-644 Migration Guide to 5 Volt Intel^®StrataFlash™ Memory

Intel^®Flash Memory Chip Scale Package User’s Guide

Preliminary Mechanical Specification for Easy BGA Package

NOTE:

1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International

customers should contact their local Intel or distribution sales office.

2. Visit Intel’s World Wide Web home page at http://www.intel.com for technical documentation and tools.

3. For the most current information on Intel StrataFlash memory, visit our website at http://developer.intel.com/

design/flash/isf.

4. This document is available on the web at http://developer.intel.com/design/flcomp/packdata/298049.htm.

52

Preliminary

型号：	28F128
PDF下载：	下载PDF文件查看货源
内容描述：	3伏特英特尔StrataFlash闪存 [3 Volt Intel StrataFlash Memory]
分类和应用：	闪存
文件页数/大小：	58 页 / 355 K
品牌：	INTEL [ INTEL ]

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