28F128J3A, 28F640J3A, 28F320J3A
Revision History
Date of Revision
Version
Description
07/07/99
08/03/99
09/07/99
-001
-002
-003
Original Version
A –A indicated on block diagram
0
2
Changed Minimum Block Erase time,I , I , Page Mode and Byte
Mode currents. Modified RP# on AC Waveform for Write Operations
OL OH
12/16/99
-004
Changed Block Erase time and t
AVWH
Removed all references to 5 V I/O operation
Corrected Ordering Information, Valid Combinations entries
Changed Min program time to 211 µs
Added DU to Lead Descriptions table
Changed Chip Scale Package to Ball Grid Array Package
Changed default read mode to page mode
Removed erase queuing from Figure 10, Block Erase Flowchart
03/16/00
-005
Added Program Max time
Added Erase Max time
Added Max page mode read current
Moved tables to correspond with sections
Fixed typographical errors in ordering information and DC parameter
table
Removed V
setting and changed V
to V
CCQ2/3 CCQ1/2
CCQ1
Added recommended resister value for STS pin
Change operation temperature range
Removed note that rp# could go to 14 V
Removed V of 0.45 V
OL
Removed V of 2.4 V
OH
Updated I
Typ values
CCR
Added Max lock-bit program and lock times
Added note on max measurements
06/26/00
2/15/01
-006
-007
Updated cover sheet statement of 700 million units to one billion.
Corrected Table 10 to show correct maximum program times.
Corrected error in Max block program time in section 6.7
Corrected typical erase time in section 6.7
Updated cover page to reflect 100K minimum erase cycles.
Updated cover page to reflect 110 ns 32M read speed.
Removed Set Read Configuration command from Table 4.
Updated Table 8 to reflect reserved bits are 1-7; not 2-7.
Updated Table 16 bit 2 definition from R to PSS.
Changed V
Max voltage from 0.8 V to 2.0 V, Section 6.4, DC
PENLK
Characteristics
Updated 32Mbit Read Parameters R1, R2 and R3 to reflect 110ns, Sec-
tion 6.5, AC Characteristics–Read-Only Operations (1,2)
Updated write parameter W13 (t
) from 90 ns to 500 ns, Section
WHRL
6.6, AC Characteristics–Write Operations
Updated Max. Program Suspend Latency W16 (t
) from 30 to 75
WHRH1
µs, Section 6.7, Block Erase, Program, and Lock-Bit Configuration Per-
formance (1,2,3)
04/13/01
-008
Revised Section 7.0, Ordering Information
Preliminary
v
INTEL [ INTEL ]
