28F008SA
Write
COMMAND DEFINITIONS
Writes to the Command User Interface enable read-
ing of device data and Intelligent Identifiers. They
also control inspection and clearing of the Status
When V
is applied to the V
pin, read opera-
PP
PPL
tions from the Status Register, intelligent identifiers,
or array blocks are enabled. Placing V on V
PPH
PP
e
Register. Additionally, when V
V
, the Com-
PPH
enables successful byte write and block erase oper-
ations as well.
PP
mand User Interface controls block erasure and byte
write. The contents of the interface register serve as
input to the internal state machine.
Device operations are selected by writing specific
commands into the Command User Interface. Table
3 defines the 28F008SA commands.
The Command User Interface itself does not occupy
an addressable memory location. The interface reg-
ister is a latch used to store the command and ad-
dress and data information needed to execute the
command. Erase Setup and Erase Confirm com-
mands require both appropriate command data and
an address within the block to be erased. The Byte
Write Setup command requires both appropriate
command data and the address of the location to be
written, while the Byte Write command consists of
the data to be written and the address of the loca-
tion to be written.
Read Array Command
Upon initial device powerup and after exit from deep
powerdown mode, the 28F008SA defaults to Read
Array mode. This operation is also initiated by writing
FFH into the Command User Interface. Microproces-
sor read cycles retrieve array data. The device re-
mains enabled for reads until the Command User
Interface contents are altered. Once the internal
Write State Machine has started a block erase or
byte write operation, the device will not recognize
the Read Array command, until the WSM has com-
pleted its operation. The Read Array command is
The Command User Interface is written by bringing
Ý
WE to a logic-low level (V ) while CE is low.
Addresses and data are latched on the rising edge
Ý
of WE . Standard microprocessor write timings are
used.
Ý
IL
e
functional when V
V
or V
.
PPH
PP
PPL
Refer to AC Write Characteristics and the AC Wave-
forms for Write Operations, Figure 11, for specific
timing parameters.
Table 4. Status Register Definitions
WSMS
7
ESS
6
ES
5
BWS
4
VPPS
R
2
R
1
R
0
3
e
e
e
e
e
e
e
e
e
SR.7
WRITE STATE MACHINE STATUS
Ready
Busy
NOTES:
1
0
Ý
RY/BY or the Write State Machine Status bit must first
be checked to determine byte write or block erase com-
pletion, before the Byte Write or Erase Status bit are
checked for success.
SR.6
ERASE SUSPEND STATUS
Erase Suspended
Erase in Progress/Completed
1
0
If the Byte Write AND Erase Status bits are set to ‘‘1’’s
during a block erase attempt, an improper command se-
quence was entered. Attempt the operation again.
SR.5
ERASE STATUS
Error in Block Erasure
Successful Block Erase
1
0
If V low status is detected, the Status Register must be
PP
e
e
e
e
e
e
SR.4
BYTE WRITE STATUS
Error in Byte Write
Successful Byte Write
cleared before another byte write or block erase opera-
tion is attempted.
1
0
The V
PP
Status bit, unlike an A/D converter, does not
provide continuous indication of V level. The WSM in-
SR.3
V
PP
V
PP
V
PP
e
STATUS
Low Detect; Operation Abort
OK
PP
1
0
terrogates the V level only after the byte write or block
PP
erase command sequences have been entered and in-
forms the system if V has not been switched on. The
V
PP
Status bit is not guaranteed to report accurate feed-
SR.2–SR.0
RESERVED FOR FUTURE
ENHANCEMENTS
PP
back between V
and V
.
PPH
PPL
These bits are reserved for future use and
should be masked out when polling the Status
Register.
12
INTEL [ INTEL ]
