28F008SA
The first task is to write the appropriate read mode
command to the Command User Interface (array, in-
telligent identifier, or Status Register). The
28F008SA automatically resets to Read Array mode
upon initial device powerup or after exit from deep
powerdown. The 28F008SA has four control pins,
two of which must be logically active to obtain data
Data Protection
Depending on the application, the system designer
may choose to make the V power supply switcha-
PP
ble (available only when memory byte writes/block
erases are required) or hardwired to V
e
. When
PPH
, memory contents cannot be altered.
V
PP
V
PPL
Ý
at the outputs. Chip Enable (CE ) is the device se-
lection control, and when active enables the select-
The 28F008SA Command User Interface architec-
ture provides protection from unwanted byte write or
block erase operations even when high voltage is
Ý
ed memory device. Output Enable (OE ) is the data
input/output (DQ –DQ ) direction control, and when
applied to V . Additionally, all functions are dis-
PP
abled whenever V is below the write lockout volt-
0
7
active drives data from the selected memory onto
CC
Ý
Ý
the I/O bus. RP and WE must also be at V
Figure 10 illustrates read bus cycle waveforms.
.
IH
Ý
, or when RP is at V . The 28F008SA
IL
age V
LKO
accommodates either design practice and encour-
ages optimization of the processor-memory inter-
face.
Output Disable
The two-step byte write/block erase Command User
Interface write sequence provides additional soft-
ware write protection.
Ý
With OE at a logic-high level (V ), the device out-
puts are disabled. Output pins (DQ –DQ ) are
placed in a high-impedance state.
IH
0
7
BUS OPERATION
Standby
Flash memory reads, erases and writes in-system
via the local CPU. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.
Ý
CE at a logic-high level (V ) places the 28F008SA
IH
in standby mode. Standby operation disables much
of the 28F008SA’s circuitry and substantially reduc-
es device power consumption. The outputs (DQ –
0
DQ ) are placed in a high-impedence state indepen-
Ý
lected during block erase or byte write, the device
will continue functioning and consuming normal ac-
tive power until the operation completes.
7
dent of the status of OE . If the 28F008SA is dese-
Read
The 28F008SA has three read modes. The memory
can be read from any of its blocks, and information
can be read from the intelligent identifier or Status
Register. V can be at either V
PP
or V
.
PPH
PPL
Table 2. Bus Operations
Ý
Ý
Ý
Ý
Ý
Mode
Read
Notes
RP
CE
OE
WE
A
V
DQ
RY/BY
0
PP
0–7
1,2,3
1,2,3
1,2,3
1,2
V
V
V
V
V
V
V
V
X
X
X
X
X
X
X
X
D
OUT
X
X
X
IH
IL
IL
IH
IH
Output Disable
V
IH
X
X
X
High Z
High Z
High Z
89H
IH
IH
IL
Standby
V
X
X
IH
Deep PowerDown
Intelligent Identifier (Mfr)
Intelligent Identifier (Device)
V
X
X
X
V
V
V
IL
IH
IH
IH
OH
OH
1,2
V
V
V
V
V
V
V
V
V
IL
IL
IL
IL
IL
IL
IH
IH
IH
1,2
V
V
V
IH
A2H
OH
X
Write
1,2,3,4,5
V
V
X
D
IN
IL
NOTES:
1. Refer to DC Characteristics. When V
e
2. X can be V or V for control pins and addresses, and V
V
PPL
, memory contents can be read but not written or erased.
for V . See DC Characteristics for V
PP
PP
or V
and V
PPL PPH
IL IH
PPL
PPH
voltages.
3. RY/BY is V when the Write State Machine is executing internal block erase or byte write algorithms. It is V
Ý
the WSM is not busy, in Erase Suspend mode or deep powerdown mode.
when
OL
OH
e
4. Command writes involving block erase or byte write are only successfully executed when V
5. Refer to Table 3 for valid D during a write operation.
IN
V
PPH
.
PP
10
INTEL [ INTEL ]
