E
1.0
SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE
INTRODUCTION
1.1
Smart 3 Advanced Boot Block
Flash Memory Enhancements
This
preliminary
datasheet
contains
the
specifications for the Advanced Boot Block flash
memory family, which is optimized for low power,
portable systems. This family of products features
1.8V–2.2V or 2.V–3.6V I/Os and a low V
CC
/V
PP
operating range of 2.7V–3.6V for read and
program/erase operations. In addition this family is
capable of fast programming at 12V. Throughout
this document, the term “2.7V” refers to the full
voltage range 2.7V–3.6V (except where noted
otherwise) and “V
PP
= 12V” refers to 12V ±5%.
Section 1 and 2 provides an overview of the flash
memory family including applications, pinouts and
pin descriptions. Section 3 describes the memory
organization and operation for these products.
Finally, Sections 4, 5, 6 and 7 contain the
operating specifications.
The new 8-Mbit and 16-Mbit Smart 3 Advanced
Boot Block flash memory provides a convenient
upgrade from and/or compatibility to previous 4-
Mbit and 8-Mbit Boot Block products. The Smart 3
product functions are similar to lower density
products in both command sets and operation,
providing similar pinouts to ease density upgrades.
The Smart 3 Advanced Boot Block flash memory
features
•
•
•
Enhanced blocking for easy segmentation of
code and data or additional design flexibility
Program Suspend command which permits
program suspend to read
WP# pin to lock and unlock the upper two (or
lower two, depending on location) 8-Kbyte
blocks
V
CCQ
input for 1.8V–2.2V on all I/Os. See
Figures 1–3 for pinout diagrams and V
CCQ
location
Maximum program time
improved data storage.
specification
for
•
•
Table 1. Smart 3 Advanced Boot Block Feature Summary
Feature
V
CC
Read Voltage
V
CCQ
I/O Voltage
V
PP
Program/Erase Voltage
Bus Width
Speed
Memory Arrangement
Blocking (top or bottom)
28F016B3/28F008B3/28F004B3
2.7V– 3.6V
1.8V–2.2V or 2.7V– 3.6V
2.7V– 3.6V or 11.4V– 12.6V
8 bits
120 ns
1 Mbit x 8 (8 Mbit), 2 Mbit x 8 (16 Mbit)
Eight 8-Kbyte parameter blocks (8/16 Mbit) &
Fifteen 64-Kbyte blocks (8 Mbit)
Thirty-one 64-Kbyte main blocks (16 Mbit)
WP# locks/unlocks parameter blocks
All other blocks protected using V
PP
switch
Extended: –40°C to +85°C
10,000 cycles
40-Lead TSOP, 48-Ball
µBGA*
CSP
Section 2.2
Figures 4 and 5
Section 3.3
Table 8
Table 9, Table 12
Table 9, Table 12
Figures 1, 2, and 3
Reference
Table 9, Table 12
Table 9, Table 12
Table 9, Table 12
Table 2
Table 15
Locking
Operating Temperature
Program/Erase Cycling
Packages
PRELIMINARY
5
INTEL [ INTEL CORPORATION ]
