E
4-Mbit: A
0
- A
18
,
8-Mbit: A
0
- A
19
,
16-Mbit: A
0
- A
20
Input
Buffer
Y
Decoder
Address
Latch
X
Decoder
Address
Counter
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
DQ
0
- DQ
7
Output
Buffer
Input
Buffer
Identifier
Register
Status
Register
Command
Register
I/O Logic
V
CC
CE#
WE#
OE#
RP#
Data
Comparator
Y Gating
Write State
Machine
RY/BY#
Program/Erase
Voltage Switch
V
PP
4-Mbit: Eight
8-Mbit: Sixteen
16-Mbit: Thirty-Two
64-Kbyte Blocks
V
CC
GND
Figure 1. Block Diagram
Table 2. Pin Descriptions
Sym
A
0
–A
20
Type
INPUT
Name and Function
ADDRESS INPUTS:
Inputs for addresses during read and write operations.
Addresses are internally latched during a write cycle.
4 Mbit
→
A
0
–A
18
8 Mbit
→
A
0
–A
19
16 Mbit
→
A
0
–A
20
DQ
0
–DQ
7
INPUT/
DATA INPUT/OUTPUTS:
Inputs data and commands during CUI write cycles;
OUTPUT outputs data during memory array, status register, and identifier code read cycles.
Data pins float to high-impedance when the chip is deselected or outputs are
disabled. Data is internally latched during a write cycle.
INPUT
CHIP ENABLE:
Activates the device’s control logic, input buffers, decoders, and
sense amplifiers. CE#-high deselects the device and reduces power consumption to
standby levels.
RESET/DEEP POWER-DOWN:
When driven low, RP# inhibits write operations
which provides data protection during power transitions, puts the device in deep
power-down mode, and resets internal automation. RP#-high enables normal
operation. Exit from deep power-down sets the device to read array mode.
RP# at V
HH
enables setting of the master lock-bit and enables configuration of block
lock-bits when the master lock-bit is set. RP# = V
HH
overrides block lock-bits,
thereby enabling block erase and program operations to locked memory blocks.
Block erase, program, or lock-bit configuration with V
IH
< RP# < V
HH
produce
spurious results and should not be attempted.
OE#
INPUT
OUTPUT ENABLE:
Gates the device’s outputs during a read cycle.
CE#
RP#
INPUT
PRELIMINARY
7
INTEL [ INTEL CORPORATION ]
