BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
E
REVISION HISTORY
Number
-001
-002
Original version
Table 3 revised to reflect change in abbreviations from “W” for write to “P” for program.
Ordering information graphic (Appendix A) corrected: from PB = Ext. Temp. 44-Lead
PSOP to
TB
= Ext. Temp. 44-Lead PSOP.
Corrected nomenclature table (Appendix A) to reflect actual Operating Temperature/
Package information
Updated Ordering Information and table
Correction to table, Section 6.2.3. Under I
LO
Test Conditions, previously read V
IN
= V
CC
or GND, corrected to V
OUT
= V
CC
or GND
Section 6.2.7, modified Program and Block Erase Suspend Latency Times
Added
µBGA*
CSP pinout and corrected error in PSOP pinout.
Added Design Consideration for V
PP
Program and Erase Voltages on future sub-0.4µ
devices.
Description
-003
4
PRELIMINARY
INTEL [ INTEL CORPORATION ]
