21150
Figures
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21150 on the System Board..................................................................................2
21150 with Option Cards.......................................................................................3
21150 on the System Board..................................................................................4
21150 Downstream Data Path ..............................................................................5
21150 Pin Assignment ........................................................................................19
Flow-Through Posted Memory Write Transaction...............................................31
Downstream Delayed Write Transaction.............................................................34
Multiple Memory Write Transactions Posted and Initiated as Fast
Back-to-Back Transactions on the Target Bus.................................................................36
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Nonprefetchable Delayed Read Transaction ......................................................40
Prefetchable Delayed Read Transaction.............................................................41
Flow-Through Prefetchable Read Transaction....................................................42
Configuration Transaction Address Formats.......................................................43
Delayed Write Transaction Terminated with Master Abort..................................49
Delayed Read Transaction Terminated with Target Abort ..................................52
I/O Transaction Forwarding Using Base and Limit Addresses............................56
I/O Transaction Forwarding in ISA Mode ............................................................58
Memory Transaction Forwarding Using Base and Limit Registers .....................60
Secondary Arbiter Example.................................................................................86
Example of gpio Clock Mask Implementation on the System Board...................91
Clock Mask Load and Shift Timing......................................................................92
p_clk and s_clk Relative Timing..........................................................................95
21150 Configuration Space...............................................................................104
PCI Clock Signal AC Parameter Measurements...............................................145
PCI Signal Timing Measurement Conditions.....................................................147
208-Pin PQFP Package ....................................................................................153
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Tables
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21150 Functional Blocks .......................................................................................4
Signal Pins ............................................................................................................7
Signal Types..........................................................................................................7
Primary PCI Bus Interface Signals........................................................................8
Secondary PCI Bus Interface Signals .................................................................11
Secondary PCI Bus Interface Signals .................................................................13
General-Purpose I/O Interface Signals ...............................................................14
Clock Signals.......................................................................................................14
Reset Signals ......................................................................................................15
Miscellaneous Signals.........................................................................................16
JTAG Signals ......................................................................................................17
Signal Types........................................................................................................20
Numeric Pin Assignments ...................................................................................21
Alphabetic Pin Assignments................................................................................24
21150 PCI Transactions......................................................................................27
Write Transaction Forwarding .............................................................................29
Write Transaction Disconnect Address Boundaries............................................35
Read Transaction Prefetching.............................................................................36
Read Prefetch Address Boundaries....................................................................38
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Preliminary Datasheet
vii
INTEL [ INTEL ]
