21150
9.2.3 Bus Parking............................................................................................87
10.0
11.0
General-Purpose I/O Interface .........................................................................................89
10.1
10.2
10.3
gpio Control Registers.........................................................................................89
Secondary Clock Control.....................................................................................90
Live Insertion.......................................................................................................92
Clocks...............................................................................................................................95
11.1
11.2
11.3
Primary and Secondary Clock Inputs..................................................................95
Secondary Clock Outputs....................................................................................95
Disabling Unused Secondary Clock Outputs ......................................................96
12.0
13.0
14.0
66-Mhz Operation.............................................................................................................97
PCI Power Management ..................................................................................................99
Reset..............................................................................................................................101
14.1
14.2
14.3
Primary Interface Reset.....................................................................................101
Secondary Interface Reset................................................................................101
Chip Reset.........................................................................................................102
15.0
Configuration Space Registers.......................................................................................103
15.1
PCI-to-PCI Bridge Standard Configuration Registers .......................................105
15.1.1 Vendor ID Register—Offset 00h...........................................................105
15.1.2 Device ID Register—Offset 02h ...........................................................105
15.1.3 Primary Command Register—Offset 04h.............................................105
15.1.4 Primary Status Register—Offset 06h ...................................................107
15.1.5 Revision ID Register—Offset 08h ........................................................109
15.1.6 Programming Interface Register—Offset 09h ......................................109
15.1.7 Subclass Code Register—Offset 0Ah ..................................................109
15.1.8 Base Class Code Register—Offset 0Bh...............................................109
15.1.9 Cache Line Size Register—Offset 0Ch ................................................110
15.1.10 Primary Latency Timer Register—Offset 0Dh......................................110
15.1.11 Header Type Register—Offset 0Eh......................................................110
15.1.12 Primary Bus Number Register—Offset 18h .........................................111
15.1.13 Secondary Bus Number Register—Offset 19h.....................................111
15.1.14 Subordinate Bus Number Register—Offset 1Ah ..................................111
15.1.15 Secondary Latency Timer Register—Offset 1Bh .................................112
15.1.16 I/O Base Address Register—Offset 1Ch ..............................................112
15.1.17 I/O Limit Address Register—Offset 1Dh...............................................113
15.1.18 Secondary Status Register—Offset 1Eh ..............................................113
15.1.19 Memory Base Address Register—Offset 20h ......................................115
15.1.20 Memory Limit Address Register—Offset 22h .......................................115
15.1.21 Prefetchable Memory Base Address Register—Offset 24h .................115
15.1.22 Prefetchable Memory Limit Address Register—Offset 26h..................116
15.1.23 Prefetchable Memory Base Address Upper 32 Bits Register—
Offset 28h..........................................................................................................116
15.1.24 Prefetchable Memory Limit Address Upper 32 Bits Register—
Offset 2Ch .........................................................................................................117
15.1.25 I/O Base Address Upper 16 Bits Register—Offset 30h........................117
15.1.26 I/O Limit Address Upper 16 Bits Register—Offset 32h ........................118
Preliminary Datasheet
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