M10-DATASHEET
2015.05.04
11
Pin Capacitance
Pin Capacitance
Table 15: Pin Capacitance for MAX 10 Devices—Preliminary
Symbol
Parameter
Value
Unit
pF
CIOB
Input capacitance on bottom I/O pins
8
7
8
CIOLRT
CLVDSB
Input capacitance on left/right/top I/O pins
pF
Input capacitance on bottom I/O pins with dedicated LVDS
pF
output (9)
CADCL
Input capacitance on left I/O pins with ADC input (10)
9
pF
pF
CVREFLRT
Input capacitance on left/right/top dual purpose VREF pin when
used as VREF or user I/O pin (11)
48
CVREFB
Input capacitance on bottom dual purpose VREF pin when used
as VREF or user I/O pin
50
pF
CCLKB
Input capacitance on bottom dual purpose clock input pins (12)
7
6
pF
pF
CCLKLRT
Input capacitance on left/right/top dual purpose clock input
pins (12)
Internal Weak Pull-Up Resistor
All I/O pins, except configuration, test, and JTAG pins, have an option to enable weak pull-up.
(9)
(10)
(11)
Dedicated LVDS output buffer is only available at bottom I/O banks.
ADC pins are only available at left I/O banks.
When VREF pin is used as regular input or output, Fmax performance is reduced due to higher pin capacitance. Using the VREF pin capacitance
specification from device datasheet, perform SI analysis on your board setup to determine the Fmax of your system.
10M40 and 10M50 devices have dual purpose clock input pins at top/bottom I/O banks.
(12)
MAX 10 FPGA Device Datasheet
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