M10-OVERVIEW
2014.09.22
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Embedded Memory Blocks
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DSP IP cores:
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Common DSP processing functions such as finite impulse response (FIR), fast Fourier transform
(FFT), and numerically controlled oscillator (NCO) functions
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Suites of common video and image processing functions
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Complete reference designs for end-market applications
DSP Builder interface tool between the Quartus II software and the MathWorks Simulink and
MATLAB design environments
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DSP development kits
Embedded Memory Blocks
Each M9K memory block of the MAX 10 device provides 9 Kb of on-chip memory capable of operating at
up to 284 MHz. The embedded memory structure consists of M9K memory blocks columns. You can
configure the columns of the embedded M9K memory blocks as either one of the following:
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RAM
First-in first-out (FIFO) buffers
ROM
The MAX 10 device memory blocks are optimized for applications such as high throughput packet
processing, embedded processor program, and embedded data storage.
You can utilize the M9K memory blocks using the following options:
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Parameterize relevant IP cores with the Quartus II parameter editor
Infer the multipliers directly with VHDL or Verilog
Table 10: M9K Supported Operation Modes and Configurations
M9K Operation Modes
Port Widths Configuration
Single-port
×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36
×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36
×1, ×2, ×4, ×8, ×9, ×16, and ×18
Simple dual-port
True dual-port
Clocking and PLL
MAX 10 devices support up to 20 global clock (GCLK) networks with operating frequency up to
450 MHz. The GCLK networks have high drive strength and low skew.
MAX 10 devices have built-in internal oscillator.
The high precision and low jitter PLLs have the following usages:
MAX 10 FPGA Device Overview
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