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10M50SAE144I7G 参数 Datasheet PDF下载

10M50SAE144I7G图片预览
型号: 10M50SAE144I7G
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, PQFP144, 22 X 22 MM, 0.50 MM PITCH, ROHS COMPLIANT, PLASTIC, EQFP-144]
分类和应用: 时钟可编程逻辑
文件页数/大小: 14 页 / 604 K
品牌: INTEL [ INTEL ]
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M10-OVERVIEW  
2014.09.22  
10  
User Flash Memory  
Feature  
Description  
Up to 17 single-ended external inputs for  
single ADC devices  
One dedicated analog and 16 dual function input pins  
Up to 18 single-ended external inputs for  
dual ADC devices  
One dedicated analog and eight dual function input pins  
in each ADC block  
Simultaneous measurement capability for dual ADC  
devices  
On-chip temperature sensor  
Monitors external temperature data input with a sampling  
rate of up to 50 kilosamples per second  
User Flash Memory  
The user flash memory (UFM) block in MAX 10 devices stores non-volatile information.  
The UFM provides an ideal storage solution that you can access using the following protocols:  
Avalon Memory Mapped (Avalon-MM) slave interface to UFM  
SPI slave interface through Avalon-MM to UFM (available in version 14.1 of the Quartus II software  
onwards)  
Table 9: UFM Features  
Features  
Capacity  
Up to 10,000 times read and write cycle counts  
Maximum 116 MHz  
Endurance  
Operating frequency  
Data length storage  
Up to 32-bit length  
Embedded Multipliers and Digital Signal Processing Support  
MAX 10 devices support up to 144 embedded multiplier blocks. Each block supports one individual  
18 × 18-bit multiplier or two individual 9 × 9-bit multipliers.  
In addition to embedded multipliers, the MAX 10 device includes a combination of on-chip resources and  
external interfaces to increase performance, reduce system cost, and lower the power consumption of  
digital signal processing (DSP) systems. You can use the MAX 10 device on its own or as a DSP device co-  
processor to improve price-to-performance ratios of DSP systems.  
You can control the operation of the embedded multiplier blocks using the following options:  
Parameterize relevant IP cores with the Quartus II parameter editor  
Infer the multipliers directly with VHDL or Verilog  
System design features provided for MAX 10 devices:  
MAX 10 FPGA Device Overview  
Send Feedback  
Altera Corporation