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10AX057H4F34I3SG 参数 Datasheet PDF下载

10AX057H4F34I3SG图片预览
型号: 10AX057H4F34I3SG
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 570000-Cell, CMOS, PBGA1152, 35 X 35 MM, ROHS COMPLIANT, FBGA-1152]
分类和应用: 可编程逻辑
文件页数/大小: 110 页 / 1391 K
品牌: INTEL [ INTEL ]
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A10-DATASHEET  
2015.12.31  
15  
Pin Capacitance  
The definitions for the equation are as follows:  
The ROCT value calculated shows the range of OCT resistance with the variation of temperature and VCCIO  
RSCAL is the OCT resistance value at power-up.  
.
ΔT is the variation of temperature with respect to the temperature at power up.  
ΔV is the variation of voltage with respect to the VCCIO at power up.  
dR/dT is the percentage change of RSCAL with temperature.  
dR/dV is the percentage change of RSCAL with voltage.  
Pin Capacitance  
Table 11: Pin Capacitance for Arria 10 Devices—Preliminary  
Symbol  
Description  
Value  
2.5  
Unit  
pF  
CIO_COLUMN  
COUTFB  
Input capacitance on column I/O pins  
Input capacitance on dual-purpose clock output/feedback pins  
2.5  
pF  
Internal Weak Pull-Up and Weak Pull-Down Resistor  
All I/O pins, except configuration, test, and JTAG pins, have an option to enable weak pull-up. The weak pull-down feature is only available for the  
pins as described in the Internal Weak Pull-Down Resistor Values for Arria 10 Devices table.  
Arria 10 Device Datasheet  
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Altera Corporation