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10AX057H4F34I3SG 参数 Datasheet PDF下载

10AX057H4F34I3SG图片预览
型号: 10AX057H4F34I3SG
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 570000-Cell, CMOS, PBGA1152, 35 X 35 MM, ROHS COMPLIANT, FBGA-1152]
分类和应用: 可编程逻辑
文件页数/大小: 110 页 / 1391 K
品牌: INTEL [ INTEL ]
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A10-DATASHEET  
2015.12.31  
14  
OCT Without Calibration Resistance Tolerance Specifications  
Resistance Tolerance  
Symbol  
Description  
Condition (V)  
Unit  
–E1, –I1  
–E2, –I2  
50  
–E3, –I3  
50  
VCCIO = 1.5, 1.35, 1.25  
VCCIO = 1.2  
–50 to +30  
–50 to +30  
–50 to +30  
–50 to +30  
–50 to +30  
–40 to +30  
–50 to +30  
–50 to +30  
–50 to +30  
%
%
%
%
%
%
%
%
%
Internal series termination without  
calibration  
40-Ω RS  
50  
50  
(40-Ω setting)  
POD12 I/O standard  
VCCIO = 1.2  
50  
50  
50  
50  
Internal series termination without  
calibration(48-Ω setting)  
48-Ω RS  
POD12 I/O standard  
VCCIO = 2.5, 3.0  
VCCIO = 1.8, 1.5  
VCCIO = 1.2  
50  
50  
40  
40  
Internal series termination without  
calibration  
50-Ω RS  
60-Ω RS  
50  
50  
(50-Ω setting)  
50  
50  
Internal series termination without VCCIO = 1.2  
50  
50  
calibration  
(60-Ω setting)  
100-Ω RD  
120-Ω RS  
Internal differential termination  
(100-Ω setting)  
VCCIO = 1.8, 1.5  
25  
35  
50  
40  
50  
%
%
Internal series termination without VCCIO = 1.2  
–50 to +30  
calibration  
(120-Ω setting)  
Figure 1: Equation for OCT Variation Without Recalibration—Preliminary  
Arria 10 Device Datasheet  
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Altera Corporation