A10-DATASHEET
2015.12.31
91
Remote System Upgrades
Active Serial (108)
Fast Passive Parallel (109)
Variant
Product Line
Width
DCLK (MHz) Minimum Configuration
Time (ms)
Width
DCLK (MHz) Minimum Configuration Time
(ms)
SX 016
SX 022
SX 027
SX 032
SX 048
SX 057
SX 066
4
4
4
4
4
4
4
100
100
100
100
100
100
100
204.81
204.81
306.48
306.48
443.35
632.08
632.08
32
32
32
32
32
32
32
100
100
100
100
100
100
100
25.60
25.60
38.31
38.31
55.42
79.01
79.01
Arria 10 SX
Related Information
•
•
Configuration Files on page 88
DCLK Frequency Specification in the AS Configuration Scheme on page 86
Provides the DCLK frequency using internal oscillator.
Remote System Upgrades
Table 84: Remote System Upgrade Circuitry Timing Specifications for Arria 10 Devices—Preliminary
Parameter
Minimum
Maximum
Unit
(110)
fMAX_RU_CLK
—
40
MHz
(108)
The minimum configuration time is calculated based on DCLK frequency of 100 MHz. Only external CLKUSRmay guarantee the frequency accuracy
of 100 MHz. If you use internal oscillator of 100 MHz, you may not get the actual frequency of 100 MHz. For the DCLK frequency using internal
oscillator, refer to the DCLK Frequency Specification in the AS Configuration Scheme table.
Maximum FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic.
Maximum FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic.
This clock is user-supplied to the remote system upgrade circuitry. If you are using the ALTREMOTE_UPDATE megafunction IP core, the clock
user-supplied to the ALTREMOTE_UPDATE IP core must meet this specification.
(109)
(109)
(110)
Arria 10 Device Datasheet
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