A10-DATASHEET
2015.12.31
86
DCLK Frequency Specification in the AS Configuration Scheme
•
AS Configuration Timing
Provides the AS configuration timing waveform.
DCLK Frequency Specification in the AS Configuration Scheme
Table 79: DCLK Frequency Specification in the AS Configuration Scheme—Preliminary
This table lists the internal clock frequency specification for the AS configuration scheme.
The DCLKfrequency specification applies when you use the internal oscillator as the configuration clock source.
The AS multi-device configuration scheme does not support DCLKfrequency of 100 MHz.
You can only set 12.5, 25, 50, and 100 MHz in the Quartus Prime software.
Parameter
Minimum
5.3
Typical
7.9
Maximum
12.5
Unit
MHz
MHz
MHz
MHz
10.6
15.7
31.4
62.9
25.0
DCLK frequency in AS configuration
scheme
21.3
50.0
42.6
100.0
PS Configuration Timing
Table 80: PS Timing Parameters for Arria 10 Devices—Preliminary
Symbol
Parameter
nCONFIGlow to CONF_DONElow
nCONFIGlow to nSTATUSlow
nCONFIGlow pulse width
Minimum
Maximum
Unit
tCF2CD
tCF2ST0
tCFG
tSTATUS
tCF2ST1
—
—
2
600
600
ns
ns
μs
μs
μs
—
nSTATUSlow pulse width
268
—
3,000 (102)
3,000 (103)
nCONFIGhigh to nSTATUShigh
(102)
(103)
This value is applicable if you do not delay configuration by extending the nCONFIGor nSTATUSlow pulse width.
This value is applicable if you do not delay configuration by externally holding the nSTATUSlow.
Arria 10 Device Datasheet
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