IZ0065
PIN DESCRIPTION
PIN №
INP/
NAME
DESCRIPTION
INTER-
FACE
Power
OUTP
VDD (24)
Operating Voltage
For logical circuit (+5 V ± 10%, +3 V ± 10%)
0 V (GND)
GND (34) Power
Supply
VEE (31)
Negative Supply
Voltage
For LCD driver circuit (-5 V)
V1 V2
(44,45)
SC1÷SC20
V3 V4
Input
Bias Voltage
Bias voltage level for LCD drive (select level)
Power
Output
LCD driver
LCD driver output
Bias voltage level for LCD drive (nonselect level)
LCD
Power
Input PART 1 Bias Voltage
(46,47)
SHL1
Input
Data interface Selection of the shift direction of Part 1 shift register
VDD
or
VSS
(41)
SHL1
VDD
VSS
DL1
out
in
DR1
in
out
DL1,DR1 Input/
(35,36) Output
Data input/output of Part 1 shift register
Controller
or
IZ0065
Output
LCD driver
LCD driver output
SC21÷
SC40
V5 V6
(48,49)
SHL2
(42)
Input PART 2 Bias Voltage
Input
Bias voltage level for LCD drive (nonselect level)
Power
Data interface Selection of the shift direction of Part 2 shift register
VDD
or
VSS
SHL2
VDD
DL2
out
in
DR2
in
out
VSS
DL2,DR2 Input/
(37,38) Output
Data input/output of Part 2 shift register
Controller
or
IZ0065
M
(40)
Input
Alternated
signal for LCD
PART FCS
CL1
CL2
M
Controller
polarity
driver output
1
2
VSS
VDD
VSS
VDD
latch clock shift clock
M
CL1,CL2 Input
Data shift / latch clock
(
)
(
)
(32,33)
shift clock latch clock
_
M
FCS
(43)
Input
Mode selection
(
)
(
)
Shift/latch clock of display data and polarity of M signal
are changed by FCS signal.
By setting FCS to VDD level , user can select the function
that use Part 1 as segment driver and Part 2 as common
driver simultaneously.
NC(39)
No connection pin
N.C
IN TEG R A L
4
INTEGRAL [ INTEGRAL CORP. ]
