IZ0065
ELECTRICAL CHARACTERISTICS
DC characteristics (VDD=2.7~5.5V, VDD - VEE =3~13V, VSS=0V, Ta=-30 ~ +85OC )
Characteristic
Symbol
Test Condition
Min
Max
Unit
Applicable pin
Operating Current *
Supply Current *
IDD
IEE
fCL2=400KHz
fCL1=1KHz
-
-
-
1
mA
µA
V
-
10
Input High Voltage
VIH
0.7VDD
VDD
CL1, CL2, DL1,
DL2,
Input Low Voltage
VIL
0
0.3VDD
5
DR1, DR2,
Input Leakage Current
ILKG
VIN =0-VDD
IOH = -0.4mA
IOL = +0.4mA
-5
SHL1, SHL2, M,
FCS
µA
Output High Voltage
VOH
VDD
0.4
-
-
DL1, DL2, DR1,
DR2
Output Low Voltage
Voltage Descending
VOL
VD1
-
-
0.4
1.1
V
ION=0.1mA for one of
SC1-SC40
V(V1-V6),
SC(SC1-SC40)
VD2
IV
ION=0.5mA for each
SC1-SC40
-
1.5
10
Leakage Current
* VDD-VEE=4V
VIH= VDD~ VEE
-10
V1-V6
µA
(Output SC1-
SC40:floating)
AC characteristics (VDD=2.7~5.5V, VDD - VEE =3~13V, VSS=0V, Ta=-30 ~ +85OC )
Characteristic
Symbol
Test Condition
Min
Max
Unit
Applicable pin
Data Shift Frequency
Clock High Level Width
Clock Low Level Width
Clock Set-up Time
fCL
tWCKH
tWCKL
tLS
-
-
400
KHz
CL2
CL1, CL2
CL2
-
800
800
500
500
-
-
-
-
from CL2 to CL1
-
-
tLS
from CL1 to CL2
ns
CL1, CL2
Clock Rise/Fall Time
Data Set-up Time
tR/tF
tSU
-
-
200
-
300
DL1, DL2, DR1,
DR2,
Data Hold Time
Data Delay Time
tDH
tD
-
300
-
-
FLM
CL=15pF
500
DL1, DL2, DR1,
DR2
Input/Output current excluded; When input is at the intermediate level with CMOS, excessive current flows through
the input circuit to the power supply,To avoid this, input level must be fixed at «H» or «L».
IN TEG R A L
2
INTEGRAL [ INTEGRAL CORP. ]
