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IN74HCT373ADW 参数 Datasheet PDF下载

IN74HCT373ADW图片预览
型号: IN74HCT373ADW
PDF下载: 下载PDF文件 查看货源
内容描述: 八路三态同相透明锁存器高性能硅栅CMOS [Octal 3-State Noninverting Transparent Latch High-Performance Silicon-Gate CMOS]
分类和应用: 锁存器
文件页数/大小: 5 页 / 119 K
品牌: INTEGRAL [ INTEGRAL CORP. ]
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IN74HCT373A
AC ELECTRICAL CHARACTERISTICS
(V
CC
=5.0 V
±
10%, C
L
=50pF,Input t
r
=t
f
=6.0 ns)
Guaranteed Limit
Symbol
Parameter
25
°C
to
-55°C
28
32
30
35
12
10
15
≤85°C
≤125°C
Unit
t
PLH
, t
PHL
t
PLH
, t
PHL
t
PLZ
, t
PHZ
t
PZL
, t
PZH
t
TLH
, t
THL
C
IN
C
OUT
Maximum Propagation Delay, Input D to Q
(Figures 1 and 5)
Maximum Propagation Delay , Latch Enable to Q
(Figures 2 and 5)
Maximum Propagation Delay ,Output Enable to Q
(Figures 3 and 6)
Maximum Propagation Delay , Output Enable to
Q (Figures 3 and 6)
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
Maximum Input Capacitance
Maximum Three-State Output Capacitance
(Output in High-Impedance State)
Power Dissipation Capacitance (Per Latch)
35
40
38
44
15
10
15
42
48
45
53
18
10
15
ns
ns
ns
ns
ns
pF
pF
Typical @25°C,V
CC
=5.0 V
65
pF
C
PD
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC2
f+I
CC
V
CC
TIMING REQUIREMENTS
(V
CC
=5.0 V
±
10%, C
L
=50pF,Input t
r
=t
f
=6.0 ns)
Guaranteed Limit
Symbol
t
SU
Parameter
Minimum Setup Time, Input D
to Latch Enable
(Figure 4)
Minimum Hold Time,Latch
Enable to Input D
(Figure 4)
Minimum Pulse Width, Latch
Enable (Figure 2)
Maximum Input Rise and Fall
Times (Figure 1)
25
°C
to
-55°C
10
≤85°C
13
≤125°C
15
Unit
ns
t
h
10
13
15
ns
t
w
t
r,
t
f
12
500
15
500
18
500
ns
ns
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