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IN74HCT373ADW 参数 Datasheet PDF下载

IN74HCT373ADW图片预览
型号: IN74HCT373ADW
PDF下载: 下载PDF文件 查看货源
内容描述: 八路三态同相透明锁存器高性能硅栅CMOS [Octal 3-State Noninverting Transparent Latch High-Performance Silicon-Gate CMOS]
分类和应用: 锁存器
文件页数/大小: 5 页 / 119 K
品牌: INTEGRAL [ INTEGRAL CORP. ]
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TECHNICAL DATA
IN74HCT373A
Octal 3-State Noninverting
Transparent Latch
High-Performance Silicon-Gate CMOS
The IN74HCT373A may be used as a level converter for
interfacing TTL or NMOS outputs to High-Speed CMOS inputs.
The IN74HCT373A is identical in pinout to the LS/ALS373.
The eight latches of the IN74HCT373A are transparent D-type
latches. While the Latch Enable is high the Q outputs follow the Data
Inputs. When Latch Enable is taken low, data meeting the setup and
hold times becomes latched.
The Output Enable does not affect the state of the latch, but when
Output Enable is high, all outputs are forced to the high-impedance
state. Thus, data may be latched even when the outputs are not
enabled.
TTL/NMOS-Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0
µA
ORDERING INFORMATION
IN74HCT373AN Plastic
IN74HCT373ADW SOIC
T
A
= -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Output
Enable
L
PIN 20=V
CC
PIN 10 = GND
L
L
H
Latch
Enable
H
H
L
X
D
H
L
X
X
Output
Q
H
L
No Change
Z
X = Don’t Care
Z = High Impedance
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