IL9270
Decoder Section
Guard Time Adjustment
The decoder uses digital counting techniques to
determine the frequencies of the limited tones and to
verify that they correspond to standard DTMF
frequencies. A complex averaging algorithm protects
against tone simulation by extraneous signals, such as
voice, while providing tolerance to small frequency
deviations and variations. This averaging algorithm has
been developed to ensure an optimum combination of
immunity to “talk-off” and tolerance to the presence of
interfering signals (“third tones”) and noise. When the
detector recognizes the simultaneous presence of two
valid tones (referred to as “signal condition” in some
industry specifications), it raises the “early steering” flag
(ESt). Any subsequent loss of signal-condition will
cause Est to fall.
In many situations not requiring independent selection of
receive and pause, the simple steering circuit of Figure 2
is applicable. Component values are chosen according to
the following formula:
tREC = tDP + tGTP
tID = tDA + tGTA
The value of tDP is a parameter of the device and tREC is
the minimum signal duration to be recognized by the
receiver. A value for C of 0.1 µF is recommended for
most applications, leaving R to be selected by the
designer. For example, a suitable value of R for a tREC of
40 ms would be 300 k.
Different steering arrangements may be esed to select
independently the guard-times for tone-present (tGTP) and
tone-absent (tGTA). This may be necessary to meet
system specifications which place both accept and reject
limits on both tone duration and inter-digital pause.
Steering Circuit
Before registration of a decoded tone-pair, the receiver
checks for a valid signal duration (referred to as
“character-recognition-condition”). This check is
performed by an external RC time-constant driven by
ESt. A logic high on ESt causes VC (see Figure 2) to rise
as the capacitor discharges. Provided signal-condition is
maintained (ESt remains high) for the validation period
(tGTP), VC reaches the threshold (VTSt) of the steering
logic to register the tone-pair, latching its corresponding
4-bit code (see Figure 3) into the output latch. At this
point, the GT output is activated and drives VC to VCC.
GT continues to drive high as long as ESt remains high.
Finally after a short delay to allow the output latch to
settle, the “delayed-steering” output flag, StD, goes high,
signaling that a received tone-pair has been registered.
The contents of the output latch are made available on
the 4-bit output bus by raising the 3-state control input
(OE) to a logic high. The steering circuit works in
reverse to validate the interdigit pause between signals.
Thus, as well as rejecting signals too short to be
considered valid, the receiver will tolerate signal
interruptions (“drop-out”) too short to be considered a
valid pause. The facility, together with the capability of
selecting the steering time-constants externally, allows
the designer to tailor performance to meet a wide variety
of system requirements.
Guard-time adjustment also allows the designer to tailor
system parameters such as talk-off and noise immunity.
Increasing tREC improves talk-off performance, since it
reduces the probability that tones simulated by speech
will maintain signal condition for long enough to be
registered. On the other hand, a relatively short tREC with
a long tDO would be appropriate for extremely noisy
environments where fast acquisition time and immunity
to drop-outs would be requirements. Design information
for guard-time adjustment is show in Figure 4.
Input Configuration
The input arrangement of the IN9270 provides a
differential-input operational amplifier as well as a bias
source (VREF) which is used to bias the inputs at mid-rail.
Provision is made for connection of a feedback resistor
to the op-amp output (GS) for adjustment of gain.
In a single-ended configuration, the input pins are
connected as shown in Figure 5 with the op-amp
connected for unity gain and VREF biasing the input at
1/2VCC. Figure 6 shows the differential configuration,
which permits the adjustment of gain with the feedback
resistor R5.
INTEGRAL [ INTEGRAL CORP. ]
