IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER
Data Sheet
TCON.3
IE1
Interrupt 1 edge flag. Set by hardware, when falling edge on
external pin INT1/ is observed Cleared when interrupt is
processed.
TCON.4
TCON.5
TR0
TF0
Timer 0 Run control bit. If cleared, Timer 0 stops.
Timer 0 overflow flag set by hardware when Timer 0
overflows. This flag should be cleared by software.
Timer 1 Run control bit. If cleared, Timer 1 stops. In mode
3 this bit controls TH0.
Timer 1 overflow flag set by hardware when Timer 1
overflows. This flag should be cleared by software.. In mode
3 this bit is controlled by TH0.
TCON.6
TCON.7
TR1
TF1
Timer 0 High byte (TH0):
High order byte of timer/counter0.
TH0
Bit: 7
6
5
4
3
2
1
0
TH0.7
TH0.6
TH0.5
TH0.4
TH0.3
TH0.2
TH0.1
TH0.0
Timer 0 Low byte (TL0):
Low order byte of timer/counter0.
TL0
Bit: 7
6
5
4
3
2
1
0
TL0.7
TL0.6
TL0.5
TL0.4
TL0.3
TL0.2
TL0.1
TL0.0
Timer 1 High byte (TH1):
High order byte of timer/counter1.
TH1
Bit: 7
6
5
4
3
2
1
0
TH1.7
TH1.6
TH1.5
TH1.4
TH1.3
TH1.2
TH1.1
TH1.0
Timer 1 Low byte (TL1):
Low order byte of timer/counter1.
TL1
Bit: 7
6
5
4
3
2
1
0
TL1.7
TL1.6
TL1.5
TL1.4
TL1.3
TL1.2
TL1.1
TL1.0
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innovASIC
ENG210010112-00
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