IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER
Data Sheet
P3.7 RD
External Data Memory read strobe, active LOW. This function is
activated by a CPU read access from External Data Memory (i.e. MOVX
A, @DPTR).
P1.6 RTS
P1.7 CTS
Request To Send output, active low.
Clear To Send input, active low.
Port Registers
Port 0 (P0):
General purpose, 8 bit, I/O port and multiplexed low order address and data bus with open-drain
output buffers.
P0
Bit: 7
6
5
4
3
2
1
0
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
Port 1 (P1):
General purpose, 8 bit, I/O port with pullups and auxiliary functions.
P1
Bit:
7
6
5
4
3
2
1
0
RTS/P1.7
CTS/P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
-
-
-
-
-
-
RTS
CTS
Request To Send output.
Clear To Send input.
Port 2 (P2):
General purpose, 8 bit, I/O port with pullups and high order address bus.
P2
Bit: 7
P2.7
6
5
P2.5
4
P2.4
3
2
P2.2
1
P2.1
0
P2.0
P2.6
P2.3
Copyright 2003
innovASIC
ENG210010112-00
www.innovasic.com
Customer Support:
1-888-824-4184
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