IA82527
Data Sheet
CAN Serial Communications Controller
December 20, 2012
Table 14. Mode 3: Asynchronous Operation Timing for 5.0V Operation
Symbol
1/tXTAL
1/tSCLK
1/tMCLK
tAVCL
Parameter
Minimum
Maximum
16 MHz
10 MHz
8 MHz
–
Oscillator Frequency
8 MHz
4 MHz
2 MHz
3 ns
System Clock Frequency
Memory Clock Frequency
Address or r-w_n Valid to cs_n Low Setup
cs_n Low to Data Valid (for High-Speed Registers 02H, 04H,
and 05H)
tCLDV
0 ns
55 ns
cs_n Low to Data Valid (for Low-Speed Registers) Read
Cycle without Previous Write
cs_n Low to Data Valid (for Low-Speed Registers) Read
Cycle with Previous Write
dsack0_n Low to Output Data Valid (for High-Speed Read
Registers)
0 ns
0 ns
–
1.5 tMCLK
100 ns
3.5 tMCLK
100 ns
23 ns
+
+
a
tKLDV
dsack0_n Low to Output Data Valid (for Low-Speed Read
Registers)
0 ns
–
tCHDV
tCHDH
tCHDZ
Input Data Hold after cs_n High
Output Data Hold after cs_n High
cs_n High to Output Data Float
cs_n High to dsack0_n = 2.4V (an on-chip pull-up will drive
dsack0_n to approximately 2.4V; an external pull-up is
required to drive this signal to a higher voltage)
cs_n High to dsack0_n = 2.8V
15 ns
0 ns
–
–
–
35 ns
55 ns
tCHKH
0 ns
1
tCHKH
–
150 ns
2
tCHKZ
tCHCL
tCHAI
tCHRI
tCLCH
tDVCH
tCLKL
cs_n High to dsack0_n Float
cs_n Width between Successive Cycles
cs_n High to Address Invalid
cs_n High to r-w_n Invalid
cs_n Width Low
CPU Write Data Valid to cs_n High
cs_n Low to dsack0_n Low (for High- and Low-Speed
Registers) Write Cycle without Previous Write
End of Previous Write (cs_n High) to dsack0_n Low for a
Write Cycle with a Previous Write
clkout Period (CDV is the value loaded in the CLKOUT
Register representing the clkout divisor)
0 ns
25 ns
7 ns
100 ns
–
–
–
–
–
5 ns
65 ns
20 ns
0 ns
67 ns
tCHKL
tCOPD
tCHCL
0 ns
2 tMCLK + 145
ns
b
(CDV + 1) × tOSC
clkout High Period (CDV is the value loaded in the CLKOUT
Register representing the clkout divisor)
(CDV + 1) ×
½ tOSC – 10
(CDV + 1) × ½
tOSC + 15
a
A “Read Cycle without Previous Write” is where a read cycle follows a write cycle and where the rising
edge of cs_n for the write and the falling edge of cs_n for the read are separated by at least 2 × tMCLK
A “Write Cycle with a Previous Write” is a write cycle following a previous write cycle where the rising
edge of cs_n for the first write and the rising edge of cs_n for the second write are separated by at least
.
b
2 × tMCLK
.
IA211080504-07
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