IA82527
Data Sheet
CAN Serial Communications Controller
December 20, 2012
Table 13. Mode 2: General Bus Timing for 3.3V Operation
Symbol Parameter
Minimum
Maximum
Oscillator Frequency
1/tXTAL
8 MHz
16 MHz
1/tSCLK
1/tMCLK
tAVSL
tSLAX
tELDZ
System Clock Frequency
Memory Clock Frequency
Address Valid to as Low
Address Hold after as Low
4 MHz
2 MHz
7.5 ns
10 ns
0 ns
10 MHz
8 MHz
–
–
Data Float after e Low
45 ns
e High to Data Valid for Registers 02H, 04H, 05H
e High to Data Valid (all Registers except for 02H, 04H,
05H) for Read Cycle without a Previous Write
e High to Data Valid (all Registers except for 02H, 04H,
05H) for Read Cycle with a Previous Write
Data Setup to e Low
Input Data Hold after e Low
e Low to Output Data Valid on Port 1/2
e High Time
0 ns
45 ns
1.5 tmclk + 100
–
–
a
tEHDV
ns
3.5 tmclk + 100
ns
–
–
tQVEL
tELQX
tELDV
tEHEL
30 ns
20 ns
tmclk
2 tmclk + 500 ns
45 ns
End of previous write (Last E Low) to E Low for Write
Cycle
tELEL
2 tmclk
tSHSL
tRSEH
tSLEH
tCLSL
tELCH
as High Time
Setup Time of r-w_n to e High
as Low to e High
cs_n Low to as Low
e Low to cs_n High
30 ns
30 ns
20 ns
20 ns
0 ns
–
–
–
–
–
clkout Period (CDV is the value loaded in the CLKOUT
Register representing the clkout divisor)
clkout High Period (CDV is the value loaded in the
CLKOUT Register representing the clkout divisor)
tCOPD
tCHCL
(CDV + 1) × tOSC
(CDV + 1) × ½
(CDV + 1) × ½
tOSC – 10
tOSC + 15
aA “Read Cycle without a Previous Write” is where a read cycle follows a write cycle and where
the falling edge of e for the write and the rising edge of e for the read are separated by at least
2 × tMCLK
.
IA211080504-07
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