IA82527
Data Sheet
CAN Serial Communications Controller
December 20, 2012
Table 10. Mode 0 and Mode 1: General Bus and Ready Timing for 5.0V Operation
Symbol
1/tXTAL
1/tSCLK
1/tMCLK
tAVLL
tLLAX
tLHLL
tLLRL
tCLLL
tQVWH
tWHQX
tWLWH
tWHLH
tWHCH
tRLRH
Parameter
Minimum
8 MHz
4 MHz
2 MHz
7.5 ns
10 ns
30 ns
20 ns
10 ns
27 ns
10 ns
30 ns
8 ns
Maximum
16 MHz
10 MHz
8 MHz
Oscillator Frequency
System Clock Frequency
Memory Clock Frequency
Address Valid to ale Low
Address Hold after ale Low
ale High Time
–
–
–
–
–
–
–
–
–
–
–
ale Low to rd_n Low
cs_n Low to ale Low
Data Setup to wr_n or wrh_n High
Input Data Hold after wr_n or wrh_n High
wr_n or wrh_n Pulse Width
wr_n or wrh_n High to Next ale High
wr_n or wrh_n High to cs_n High
0 ns
40 ns
rd_n Pulse Width. This time is long enough to initiate a double
read cycle by loading the High Speed Registers (04H, 05H), but is
too short to read from 04H and 05H (see tRLDV).
rd_n Low to Data Valid (only for Registers 02H, 04H, 05H)
rd_n Low Data to Data Valid (for all Registers except 02H, 04H,
tRLDV
tRLDV1
0 ns
–
55 ns
1.5 tMCLK
100 ns
+
a
05H) for Read Cycle without a Previous Write
tRLDV1
rd_n Low Data to Data Valid (for all Registers except 02H, 04H,
05H) for Read Cycle with a Previous Write
Data Float after rd_n High
cs_n Low to ready Setup (Load Capacitance on the ready Output
= 50 pF, VOL = 1.0 V)
–
3.5 tMCLK
100 ns
45 ns
+
tRHDZ
tCLYV
0 ns
–
32 ns
cs_n Low to ready Setup (Load Capacitance on the ready Output
= 50 pF, VOL = 0.45 V)
wr_n or wrh_n Low to ready Float for a Write Cycle if No Previous
Write is Pending
–
–
40 ns
tWLYZ
145 ns
End of Last Write to ready Float for a Write Cycle if a Previous
Write Cycle is Active
–
2 tMCLK
100 ns
+
HYZ
b
tRLYZ
rd_n Low to ready Float (for all registers except 02H, 04H, 05H)
for Read Cycle without a Previous Write
–
2 tMCLK
100 ns
+
a
tRLYZ
tWHDV
tCOPO
tCHCL
rd_n Low to ready Float (for all registers except 02H, 04H, 05H)
for Read Cycle with a Previous Write
wr_n or wrh_n High to Output Data Valid on Port 1 or Port 2
–
4 tMCLK
100 ns
2 tMCLK
500 ns
–
+
tMCLK
+
clkout Period (CDV is the value loaded in the CLKOUT Register
representing the clkout divisor)
clkout High Period (CDV is the value loaded in the CLKOUT
Register representing the clkout divisor)
(CDV + 1) ×
tOSC
(CDV + 1) × (CDV + 1) ×
½ tOSC – 10 ½ tOSC + 15
a
A “Read Cycle without a Previous Write” is where a read cycle follows a write cycle and there is greater
than 2×tMCLK between the rising edge of wr_n or wrh_n and the falling edge of rd_n.
b
A “Previous Write Cycle is Active” is where the rising edge of wr_n or wrh_n for the second write is less
than 2×tMCLK after the rising edge of wr_n or wrh_for the first write.
IA211080504-07
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