IA82527
Data Sheet
CAN Serial Communications Controller
December 20, 2012
Table 3. Pin/Signal Descriptions (Continued)
Pin
Signal
ste
Name
PLCC PQFP
Description
a3/ad3/ste
43
37
synchronization transmission enable. Input. Serial
interface Mode. The logic level at the ste pin enables
the transmission of the synchronization bytes through
the IA82527 miso pin while the master device
transmits the Address and Control Byte as follows:
• When a logic 0 is placed on the ste pin, the
synchronization bytes sent through the miso pin are
00H and 00H.
• When a logic 1 is placed on the ste pin, the
synchronization bytes sent through the miso pin are
AAH and 55H.
The IA82527 sends the synchronization bytes after the
cs_n signal has been asserted
tx0
tx1
tx0
tx1
26
25
20
19
Transmit (tx), lines 0 and 1. Output (push-pull). Pins
tx0 and tx1 are the outputs from the IA82527 to the
CAN bus lines.
During a recessive bit, tx0 is high and tx1 is low.
During a dominant bit, tx0 is low and tx1 is high.
VCC
VCC
1
39
18
Power (VCC). This pin provides power for the IA82527
device. It must be connected to a +5V DC power
source.
VCC/2
int_n/ VCC/2
24
Reference Voltage, ISO Physical Layer (VCC/2).
Output. The VCC/2 pin provides a reference voltage for
the ISO low-speed physical layer:
• 2.38V DC (minimum) to 2.60V DC (maximum)
(VCC = +5.0V; IOUT ≤ 75 μA)
• 1.46V DC (minimum) to 1.688V DC (maximum)
(VCC = +3.3V; IOUT ≤ 75 μA)
This pin only functions as VCC/2 when the MUX bit of
the CPU Interface Register (02H) is 1.
VSS1
VSS2
wr_n
VSS1
23
20
7
17
14
1
Ground, Digital (VSS1). This pin provides the digital
ground (0V) for the IA82527. It must be connected to
a VSS board plane.
VSS2
Ground, Analog (VSS2). This pin provides the ground
(0V) for the IA82527 analog comparator. It must be
connected to a VSS board plane.
wr_n/wrl_n/r-w_n
write. Input. Active Low. Mode 0. When wr_n is
asserted (low), it signals a write cycle.
IA211080504-07
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